公开(公告)号：US10147638B1

公开(公告)日：2018-12-04

申请号：US15858072

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20170263552A1

公开(公告)日：2017-09-14

申请号：US15606312

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L23/528 ,  H01L21/027 ,  H01L23/52 ,  H01L21/467 ,  H01L21/308 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

公开(公告)号：US09177795B2

公开(公告)日：2015-11-03

申请号：US14040245

申请日：2013-09-27

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

IPC: H01L21/302 ,  H01L21/027 ,  C08G81/00

CPC classification number: H01L21/0273 ,  B81C1/00031 ,  B81C2201/0149 ,  C08G81/00 ,  C08L53/005 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31058

Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

Abstract translation: 形成纳米结构的方法可以包括在衬底中的材料中的沟槽内形成嵌段共聚物组合物，其中嵌段共聚物组合物可以包含嵌段共聚物材料和对于嵌段共聚物材料的第一嵌段具有更高亲和力的可活化催化剂 与第二嵌段共聚物材料相比; 将嵌段共聚物组合物自组装成包含第一嵌段和可活化催化剂的第一畴，以及包含第二嵌段的第二畴; 在第一区域的至少一部分中从可活化催化剂产生催化剂以产生包含含催化剂的区域和第二区域的结构，所述含催化剂的区域包含第一嵌段和催化剂; 并使金属氧化物前体与含催化剂的区域中的催化剂反应，以制备包含第一嵌段和金属氧化物的含金属氧化物的结构。

公开(公告)号：US20150179467A1

公开(公告)日：2015-06-25

申请号：US14139582

申请日：2013-12-23

Applicant: Micron Technology, Inc. ,  Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： William R. Brown ,  Adam Olson ,  Kaveri Jain ,  Ho Seop Eom ,  Xue Gloria Chen ,  Nik Mirin ,  Dan Millward ,  Peter Trefonas, III ,  Phillip Dene Hustad ,  Jong Keun Park ,  Christopher Nam Lee

IPC: H01L21/308

CPC classification number: H01L21/0274 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

Abstract: Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material.

Abstract translation: 一些实施例包括形成图案的方法。 在材料上形成第一个掩模。 第一掩模具有在其中延伸的特征并且限定第一图案。 第一种模式在特征分布上具有第一级的均匀性。 在第一掩模之间并且在特征内形成刷层以使特征变窄以从第一掩模创建第二掩模。 所述第二掩模具有比所述第一级别的均匀性更窄的所述窄化特征的第二级别的均匀性。 图案从第二个掩模转移到材料中。

公开(公告)号：US20150091137A1

公开(公告)日：2015-04-02

申请号：US14040245

申请日：2013-09-27

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

IPC: H01L21/027 ,  C08G81/00

CPC classification number: H01L21/0273 ,  B81C1/00031 ,  B81C2201/0149 ,  C08G81/00 ,  C08L53/005 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31058

Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

Abstract translation: 形成纳米结构的方法可以包括在衬底中的材料中的沟槽内形成嵌段共聚物组合物，其中嵌段共聚物组合物可以包含嵌段共聚物材料和对于嵌段共聚物材料的第一嵌段具有更高亲和力的可活化催化剂 与第二嵌段共聚物材料相比; 将嵌段共聚物组合物自组装成包含第一嵌段和可活化催化剂的第一畴，以及包含第二嵌段的第二畴; 在第一区域的至少一部分中从可活化催化剂产生催化剂以产生包含含催化剂的区域和第二区域的结构，所述含催化剂的区域包含第一嵌段和催化剂; 并使金属氧化物前体与含催化剂的区域中的催化剂反应，以制备包含第一嵌段和金属氧化物的含金属氧化物的结构。

公开(公告)号：US20140353803A1

公开(公告)日：2014-12-04

申请号：US14457658

申请日：2014-08-12

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

IPC: H01L23/52

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

公开(公告)号：US11532477B2

公开(公告)日：2022-12-20

申请号：US16049329

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

IPC: H01L21/027 ,  C08G81/00 ,  H01L21/033 ,  H01L21/3105 ,  B81C1/00 ,  C08L53/00 ,  H01L21/02

Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

公开(公告)号：US10811355B2

公开(公告)日：2020-10-20

申请号：US16200902

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC: H01L23/528 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/033 ,  H01L21/3213 ,  H01L49/02 ,  H01L27/108 ,  G01R31/26 ,  H01L21/66 ,  G01R1/073 ,  H01L27/02 ,  H01L27/11519 ,  G06F30/39

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

公开(公告)号：US10600681B2

公开(公告)日：2020-03-24

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20190206726A1

公开(公告)日：2019-07-04

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.