公开(公告)号：US11563008B2

公开(公告)日：2023-01-24

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US11177271B2

公开(公告)日：2021-11-16

申请号：US15705179

申请日：2017-09-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11565

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US10586807B2

公开(公告)日：2020-03-10

申请号：US16437781

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11519

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US10163655B2

公开(公告)日：2018-12-25

申请号：US14948074

申请日：2015-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jin Lu ,  Rita J. Klein ,  Diem Thy N. Tran ,  Irina V. Vasilyeva ,  Zhiqiang Xie

IPC: H01L29/40 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/48

Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.