公开(公告)号：US20240071931A1

公开(公告)日：2024-02-29

申请号：US17900064

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Tom George ,  Rita J. Klein ,  Daniel Billingsley ,  Pengyuan Zheng ,  Yongjun Jeff Hu

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprising channel-material strings extend through the insulative tiers and the conductive tiers. The conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. A through-array-via (TAV) region is included and comprises TAVs individually comprising the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. The lower conductor material is directly against the conducting material and comprises at least one of (a) and (b), where, (a): a metal-rich refractory metal nitride; and (b): a stoichiometric or non-stoichiometric refractory metal nitride directly above and directly against one of (1), (2), or (3), where: (1): an elemental metal; (2): an alloy of at least two elemental metals; and (3): a metal-rich refractory metal nitride of different composition from that of the stoichiometric or non-stoichiometric refractory metal nitride. Methods are also disclosed.

公开(公告)号：US11894305B2

公开(公告)日：2024-02-06

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11742282B2

公开(公告)日：2023-08-29

申请号：US16988422

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John D. Hopkins ,  Shuangqiang Luo ,  Song Kai Tan ,  Jing Wai Fong ,  Anurag Jindal ,  Chieh Hsien Quek

IPC: H01L23/522 ,  H01L21/768 ,  H10B43/27 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877 ,  H10B43/27 ,  H01L23/53209 ,  H01L23/53266

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

公开(公告)号：US20230207458A1

公开(公告)日：2023-06-29

申请号：US18046111

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  Jay S. Brown ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Rita J. Klein

IPC: H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.

公开(公告)号：US20230164991A1

公开(公告)日：2023-05-25

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02 ,  H10B43/27 ,  H10B43/30

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/30625 ,  G11C16/0408 ,  G11C16/0466 ,  G11C5/025 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20220310525A1

公开(公告)日：2022-09-29

申请号：US17216264

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett Allen McTeer ,  John Hopkins

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; and a tungsten material located between the first and second dielectric materials and separated from the portion of the pillar and the first and second dielectric materials by an additional dielectric material. The additional dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide. The additional dielectric material contacts the portion of the pillar and the tungsten material.

公开(公告)号：US11195848B2

公开(公告)日：2021-12-07

申请号：US16550250

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US20210202710A1

公开(公告)日：2021-07-01

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US12170250B2

公开(公告)日：2024-12-17

申请号：US18157962

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/532 ,  H01L27/06

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.