-
公开(公告)号：US20180336946A1
公开(公告)日：2018-11-22
申请号：US15600851
申请日：2017-05-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Chao-I Wu , Dai-Ying Lee
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0064 , G11C2013/0042 , G11C2013/0057
Abstract: A memory operating method and a memory operating device are provided. The memory operating method includes the following steps. A first stepping loop is performed. A second stepping loop is performed. In the first stepping loop, a first control voltage applied to a first control line is increased from a first initial value to a first final value which is larger than the first initial value, and a second control voltage applied to a second control line is fixed at a second initial value. In the second stepping loop, the first control voltage applied to the first control line is fixed at a fixing value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value which is larger than the second initial value.
-
公开(公告)号：US09627058B2
公开(公告)日：2017-04-18
申请号：US14838478
申请日：2015-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu , Tien-Yen Wang
CPC classification number: G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/79
Abstract: An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value.
-
公开(公告)号：US09620210B2
公开(公告)日：2017-04-11
申请号：US15094993
申请日：2016-04-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su , Hsiang-Pang Li
CPC classification number: G11C13/0097 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/0069 , G11C29/50008 , G11C2213/79 , G11C2213/82
Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
-
公开(公告)号：US09349443B2
公开(公告)日：2016-05-24
申请号：US14210532
申请日：2014-03-14
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Chao-I Wu
IPC: G11C11/56
CPC classification number: G11C11/5671 , G11C11/5628 , G11C2211/5621
Abstract: A method and a system for programming a multi-level cell (MLC) memory are provided. A first count is 1 initially. The method comprises the following steps. A first energy is set. The first energy is applied to alter a resistance of a cell of the MLC memory. The first count is increased by 1 after performing the step of applying the first energy. In the step of setting the first energy, the first energy is a first initial energy a predetermined value initially and the first energy is changed by increasing or decreasing the first initial energy the predetermined value the first count .
Abstract translation: 提供了一种用于编程多级单元（MLC）存储器的方法和系统。 最初的计数是1。 该方法包括以下步骤。 设置第一个能量。 施加第一能量以改变MLC存储器的单元的电阻。 在执行施加第一能量的步骤之后，第一计数增加1。 在设定第一能量的步骤中，第一能量是初始的初始能量初始化能量a侯预定值，并且通过增加或减小第一能量初始化初始化 能量呃预定值先计数。
-
公开(公告)号：US20150262676A1
公开(公告)日：2015-09-17
申请号：US14210532
申请日：2014-03-14
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Chao-I Wu
CPC classification number: G11C11/5671 , G11C11/5628 , G11C2211/5621
Abstract: A method and a system for programming a multi-level cell (MLC) memory are provided. A first count is 1 initially. The method comprises the following steps. A first energy is set. The first energy is applied to alter a resistance of a cell of the MLC memory. The first count is increased by 1 after performing the step of applying the first energy. In the step of setting the first energy, the first energy is a first initial energy a predetermined value initially and the first energy is changed by increasing or decreasing the first initial energy the predetermined value the first count .
Abstract translation: 提供了一种用于编程多级单元（MLC）存储器的方法和系统。 最初的计数是1。 该方法包括以下步骤。 设置第一个能量。 施加第一能量以改变MLC存储器的单元的电阻。 在执行施加第一能量的步骤之后，第一计数增加1。 在设置第一能量的步骤中，第一能量是最初的初始能量初始值，并且第一能量通过增加或减少第一能量初始化 能量预先计算的数值。
-
Patent Agency Ranking
公开(公告)号：US20150255126A1
公开(公告)日：2015-09-10
申请号：US14309920
申请日：2014-06-20
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su
CPC classification number: G11C29/12 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/50008 , G11C2013/0092 , G11C2029/0409 , G11C2211/563 , G11C2211/5644 , G11C2211/5646
Abstract: A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
Abstract translation: 提供了存储器件和相关联的控制方法。 存储器件包括存储单元阵列，感测单元和控制器。 存储单元具有多个存储单元。 感测单元电连接到存储单元阵列和控制器。 感测单元感测多个存储单元的存储单元的特性。 控制器确定存储单元之一的特性是否偏离，从而控制存储单元阵列。
-
公开(公告)号：US20140153326A1
公开(公告)日：2014-06-05
申请号：US13693816
申请日：2012-12-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Tien-Yen Wang , Chao-I Wu , Chun-Hsiung Hung
CPC classification number: G11C7/06 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
Abstract: A cell sensing circuit for a phase changing memory and methods thereof are provided. A specific one of the proposed methods includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell; establishing a cell voltage on a cell side and a reference voltage on a reference side respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage.
Abstract translation: 提供了一种用于相变存储器的单元感测电路及其方法。 所提出的方法中的具体方法包括：提供具有读出放大器的感测电路和分别由参考单元和目标单元接收的两个相同的稳定电流; 通过两个相同的稳定电流分别在单元侧建立电池电压和参考侧上的参考电压; 以及使用所述读出放大器基于所述参考电压和所述单元电压之间的电压差来确定所述目标单元的逻辑状态。
-
公开(公告)号：US20170206960A1
公开(公告)日：2017-07-20
申请号：US15134438
申请日：2016-04-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu , Dai-Ying Lee , Ming-Hsiu Lee , Tien-Yen Wang
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2213/52 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1633
Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
-
公开(公告)号：US09711217B1
公开(公告)日：2017-07-18
申请号：US15134438
申请日：2016-04-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu , Dai-Ying Lee , Ming-Hsiu Lee , Tien-Yen Wang
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2213/52 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1633
Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
-
公开(公告)号：US09627054B2
公开(公告)日：2017-04-18
申请号：US14711867
申请日：2015-05-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu
CPC classification number: G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0057
Abstract: A memory operating method comprises the following steps: a first read voltage is applied to the memory cell to read a first group of data levels of the memory cell; and if the data of the memory cell can not be read with the first read voltage, a second read voltage is applied to the memory cell to read a second group of data levels of the memory cell.
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.018 seconds)
