公开(公告)号：US09547586B2

公开(公告)日：2017-01-17

申请号：US13939948

申请日：2013-07-11

Applicant: Macronix International Co., Ltd.

Inventor： Hung-Sheng Chang ,  Cheng-Yuan Wang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Pi-Cheng Hsiu ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/7204 ,  G06F2212/7211

Abstract: A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.

Abstract translation: 提供了一种用于管理包括数据对象的文件系统的方法。 数据对象，间接指针和源指针存储在具有地址并包含存储器可寻址单元的容器中。 对象映射到相应容器的地址。 特定容器中的间接指针指向存储相应对象的容器的地址。 特定容器中的源指针指向特定容器中的对象映射到的容器的地址。 将第一容器中的物体移动到第二容器。 第一个容器中的源指针用于查找对象映射到的第三个容器。 第三个容器中的间接指针被更新为指向第二个容器。 第二个容器中的源指针被更新为指向第三个容器。

公开(公告)号：US09513815B2

公开(公告)日：2016-12-06

申请号：US14523006

申请日：2014-10-24

Applicant: Macronix International Co., Ltd.

Inventor： Ping-Chun Chang ,  Yuan-Hao Chang ,  Hung-Sheng Chang ,  Tei-Wei Kuo ,  Hsiang-Pang Li

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1024 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/7201

Abstract: A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.

Abstract translation: 提供了一种用于管理包括多个物理存储器段的存储器件的方法。 逻辑存储器空间根据使用规范被分类为多个分类。 基于多个分类，以及物理存储器段的使用统计，将多个物理存储器段分配给相应的逻辑地址。 数据结构保持在逻辑存储器空间中的逻辑地址和物理存储器段的物理地址之间进行记录转换。 多个分类包括与第一分类不同的使用统计要求的第一分类和第二分类。 具有第二分类的逻辑地址可以被重定向到分配给具有第一分类的逻辑地址的物理段，并且可以更新数据结构以记录重定向的逻辑地址。 免费命令可以释放分配给主内存使用的物理内存段。

公开(公告)号：US20160147464A1

公开(公告)日：2016-05-26

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

Abstract translation: 一种用于存储器的操作方法，所述存储器包括至少一个存储块，所述至少一个存储块包括与所述第一页对应的多个第一页和多个第二页，所述操作方法包括以下步骤：确定所述第一页的目标第一页 页面是有效的，其中目标第一页面对应于第二页面的目标第二页面; 如果目标第一页有效，则在目标第二页上执行第一类型编程; 如果目标第一页无效，则在目标第二页上执行第二类型编程。

公开(公告)号：US11550709B2

公开(公告)日：2023-01-10

申请号：US16655510

申请日：2019-10-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Wang ,  Hung-Sheng Chang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/02 ,  G06N3/08 ,  G06N3/10 ,  G11C7/10

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

公开(公告)号：US11443797B2

公开(公告)日：2022-09-13

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/408 ,  G11C11/4094

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US11354123B2

公开(公告)日：2022-06-07

申请号：US17026347

申请日：2020-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Han-Wen Hu ,  Yueh-Han Wu ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F7/544 ,  G06F9/345 ,  G06F9/30

Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.

公开(公告)号：US20210326114A1

公开(公告)日：2021-10-21

申请号：US17217482

申请日：2021-03-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F7/544 ,  G06N3/04 ,  G06N3/08 ,  G06F7/483 ,  G11C13/00

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

公开(公告)号：US10891077B2

公开(公告)日：2021-01-12

申请号：US16232119

申请日：2018-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hang-Ting Lue ,  Yuan-Hao Chang

IPC: G06F3/06

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

公开(公告)号：US20200312405A1

公开(公告)日：2020-10-01

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： SHU-YIN HO ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US20190050156A1

公开(公告)日：2019-02-14

申请号：US15672430

申请日：2017-08-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F12/02 ,  G11C7/04

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.