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11.发明授权Decoding apparatus, decoding method, and program to decode low density parity check codes 有权解码装置，解码方法和程序来解码低密度奇偶校验码公开(公告)号：US07299397B2
公开(公告)日：2007-11-20
申请号：US10521054
申请日：2004-04-19
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（PxP）单位矩阵，单位矩阵中的一个到数个1被0替换的矩阵，它们被循环移位的矩阵的组合形成矩阵，矩阵是 它们中的两个或更多个的和，以及（PxP）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。
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公开(公告)号：US20050240853A1
公开(公告)日：2005-10-27
申请号：US10521054
申请日：2004-04-19
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（PxP）单位矩阵，单位矩阵中的一个到数个1被0替换的矩阵，它们被循环移位的矩阵的组合形成矩阵，矩阵是 它们中的两个或更多个的和，以及（PxP）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。
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13.再颁专利Decoding apparatus, decoding method, and program to decode low density parity check codes 有权解码装置，解码方法和程序来解码低密度奇偶校验码公开(公告)号：USRE44420E1
公开(公告)日：2013-08-06
申请号：US12611227
申请日：2004-04-19
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（P×P）单位矩阵，单位矩阵中的1至数个1被0替换的矩阵，循环移位的矩阵，矩阵， 它们是两个或更多个的和，（P×P）0矩阵的和。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。
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公开(公告)号：US08437426B2
公开(公告)日：2013-05-07
申请号：US12567856
申请日：2009-09-28
申请人： Hidetoshi Kawauchi , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
发明人： Hidetoshi Kawauchi , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。
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公开(公告)号：US08045945B2
公开(公告)日：2011-10-25
申请号：US12393093
申请日：2009-02-26
申请人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
发明人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
IPC分类号： H04B1/10
CPC分类号： H04B1/1036 , H04L5/0048 , H04L25/0216 , H04L25/0232
摘要： A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.
摘要翻译： 一种接收装置，包括提取部分; 传输线特性估计部; 插值部分; 赔偿部分; 检测部; 和选择部分。
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16.发明授权公开(公告)号：US07986615B2
公开(公告)日：2011-07-26
申请号：US12403436
申请日：2009-03-13
申请人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takashi Horiguti , Naoki Yoshimochi , Yasuhiro Iida , Satoru Hori
发明人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takashi Horiguti , Naoki Yoshimochi , Yasuhiro Iida , Satoru Hori
IPC分类号： H04J11/00
CPC分类号： H04L27/2647 , H04L25/0232 , H04L25/03821
摘要： A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.
摘要翻译： 一种解调电路，包括：FFT处理部分; 一个载波间干扰部分去除部分; 提取部分; 传输路径特性估计部分; 内插部分 一个符号序列估计部分; 和干扰复制产生部分。
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公开(公告)号：US07536628B2
公开(公告)日：2009-05-19
申请号：US11354000
申请日：2006-02-15
CPC分类号： H03M13/458 , H03M13/1191 , H03M13/132 , H03M13/15 , H03M13/1515 , H03M13/152
摘要： The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.
摘要翻译： 本发明提供了一种用于对ring-R线性码进行解码处理的解码装置。 解码装置包括编码字保持装置，用于通过从编码字中省略一些符号并且用于保存编码字来获取编码字减少的编码字; 已知信息添加装置，用于附加从编码字中省略的每个符号的可靠性级别，以将其代码长度减小为已知值，作为已知值，将其作为已知信息由编码字保持装置保存的编码字; 以及重复解码装置，用于通过已知信息添加装置对包含附加到编码字的已知信息的编码字重复执行使用置信传播的解码处理。
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公开(公告)号：US06765507B2
公开(公告)日：2004-07-20
申请号：US10428905
申请日：2003-05-02
IPC分类号： H03M700
CPC分类号： H03M13/29 , H03M13/258 , H03M13/2771 , H03M13/2972
摘要： An encoding device in a data transmission/reception system includes a first convolutional encoder that encodes an outer code, an interleaver that permutes input data, a second convolutional encoder that encodes an inner code, and a muti-level modulation mapping circuit that performs signal-point mapping based on eight-phase shift keying. When the encoding device uses the second convolutional encoder having two or more memories, the first convolutional encoder uses, as the outer code, a code with a minimum output distance greater than the maximum input distance at which the minimum-distance inner code is generated.
摘要翻译： 数据发送/接收系统中的编码装置包括：对外部码进行编码的第一卷积编码器，对输入数据进行置换的交织器;对内部编码进行编码的第二卷积编码器;以及多电平调制映射电路， 基于八相移键控的点映射。 当编码装置使用具有两个或更多个存储器的第二卷积编码器时，第一卷积编码器使用具有大于产生最小距离内码的最大输入距离的最小输出距离的代码作为外码。
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公开(公告)号：US08155223B2
公开(公告)日：2012-04-10
申请号：US12562469
申请日：2009-09-18
CPC分类号： H04L25/03159 , H04L5/0048 , H04L25/0216 , H04L25/0232 , H04L27/2607 , H04L27/2647
摘要： A receiving device includes a pilot signal extractor, an estimator, an interpolator, a distortion corrector, a calculator, and a determiner.
摘要翻译： 接收装置包括导频信号提取器，估计器，内插器，失真校正器，计算器和确定器。
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公开(公告)号：US08086934B2
公开(公告)日：2011-12-27
申请号：US11912481
申请日：2006-04-20
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.
摘要翻译： 解码装置和方法能够以高精度解码LDPC码，同时防止解码装置的电路规模增加。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与三个校验节点处理相对应的第一计算处理进行处理，并将第一计算处理的结果存储在 解码中间结果存储存储器。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与六个可变节点处理相对应的第二计算处理进行解码，并将解码中间结果存储在解码中间结果 存储内存
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