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公开(公告)号：US20050240853A1
公开(公告)日：2005-10-27
申请号：US10521054
申请日：2004-04-19
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（PxP）单位矩阵，单位矩阵中的一个到数个1被0替换的矩阵，它们被循环移位的矩阵的组合形成矩阵，矩阵是 它们中的两个或更多个的和，以及（PxP）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。
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公开(公告)号：US08640010B2
公开(公告)日：2014-01-28
申请号：US12335802
申请日：2008-12-16
IPC分类号： G06F11/00
CPC分类号： H03M13/15 , H03M13/1515 , H03M13/45
摘要： Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.
摘要翻译： 本发明公开了一种对线性块码执行软判决解码的解码装置，该装置包括：硬判决解码器，被配置为使用硬判决解码算法对接收到的字执行硬判决解码; 以及软判决解码器，其被配置为仅在硬判决解码器在硬判决解码中已经失败的接收到的字上执行软判决算法的软判决解码。
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3.发明授权Information processor and information processing method, display device, and program 有权信息处理器和信息处理方法，显示设备和程序公开(公告)号：US08451966B2
公开(公告)日：2013-05-28
申请号：US12567837
申请日：2009-09-28
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.
摘要翻译： 本文公开了一种信息处理器，包括：接收部分，被配置为接收根据OFDM系统传输的OFDM信号; FFT算术运算部，被配置为对所述OFDM信号的预定间隔内的信号进行FFT; 延迟分布估计部，被配置为从所述接收部接收到的OFDM信号估计延迟分布; 符号间干扰量估计部，被配置为通过使用由所述延迟分布估计部估计出的延迟分布，分别估计所述预定间隔的多个候选的符号间干扰量; 以及搜索部，被配置为从所述预定间隔中的所述多个候选中搜索具有由所述符号间干扰量估计部估计的最小符号间干扰量的候选，并且将所搜索的候选者的数据提供为 到FFT运算部分的预定间隔。
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公开(公告)号：US08238459B2
公开(公告)日：2012-08-07
申请号：US12361199
申请日：2009-01-28
申请人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
发明人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
IPC分类号： H04L23/02
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
摘要翻译： 一种解码装置，对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码，并检测同步，解码装置包括：解码器，被配置为对作为通过解调正交调制信号而获得的解调数据的第一解调数据进行解码 并且由同相轴数据和正交轴数据组成。 解码装置对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码。 同步检测器被配置为从通过解码第一解调数据获得的第一解码数据检测预定信息符号序列之间的边界，并通过解码第二解调数据获得的第二解码数据检测边界。 同步检测器基于边界检测的结果选择并输出第一解码数据和第二解码数据中的一个。
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公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。
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6.发明申请Encoding device, encoding method, encoding method program, decoding device, decoding method, decoding method program 失效编码装置，编码方法，编码方法程序，解码装置，解码方法，解码方法程序公开(公告)号：US20050010848A1
公开(公告)日：2005-01-13
申请号：US10498936
申请日：2003-10-08
CPC分类号： H04L1/006 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2972 , H04L1/0055 , H04L1/0065 , H04L1/0071
摘要： The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.
摘要翻译： 本发明特别适用于串联编码和串行级联网格编码调制。 在作为内部编码的第二编码器107中，输出未被编码或编码以产生有限脉冲响应的序列和被编码以产生无限脉冲响应的序列。 在第二编码107之前的交织106中，将这些序列置换为不相互混合。
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公开(公告)号：US20100080330A1
公开(公告)日：2010-04-01
申请号：US12567856
申请日：2009-09-28
申请人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
发明人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
IPC分类号： H04B1/10
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。
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公开(公告)号：US20090235060A1
公开(公告)日：2009-09-17
申请号：US12403445
申请日：2009-03-13
IPC分类号： G06F9/38
CPC分类号： H03M13/41
摘要： A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.
摘要翻译： 数据处理装置包括：分支度量计算部，被配置为计算分支度量; 配置为计算状态度量的状态度量计算部分; 检测部，被配置为检测最小状态度量; 存储部，被配置为将状态存储为存活状态; 以及选择部，被配置为选择候选。
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公开(公告)号：US20090217121A1
公开(公告)日：2009-08-27
申请号：US11912481
申请日：2006-04-20
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译： 解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。 计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理，并且存储第一 在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理 并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。
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10.发明申请公开(公告)号：US20090190695A1
公开(公告)日：2009-07-30
申请号：US12361199
申请日：2009-01-28
申请人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
发明人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
IPC分类号： H03D3/00
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： Disclosed herein is a decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device including, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data, and decode second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data, and a synchronization detector configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data, the synchronization detector selecting and outputting one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
摘要翻译： 本文公开了一种解码装置，其对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码，并检测同步，该解码装置包括：解码器，被配置为对作为解调数据的第一解调数据进行解码， 正交调制信号，并且由同相轴数据和正交轴数据组成，并且对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码，以及同步检测器， 从通过对第一解调数据进行解码而获得的第一解码数据的预定信息符号序列之间的边界，并通过对第二解调数据进行解码获得的第二解码数据检测边界，同步检测器选择并输出第一解码数据和第二解码数据之一 基于de的结果 切割边界。
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