公开(公告)号：US07583555B2

公开(公告)日：2009-09-01

申请号：US10814935

申请日：2004-03-30

申请人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

发明人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

IPC分类号： G11C7/00 ,  G05F1/40

CPC分类号： G05F1/40 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.

摘要翻译： 一方面，用于电压调节的方法和装置在一个方面使用特定于所讨论的集成器件的工艺分裂的最坏情况的电源电压。 在另一方面，两相电压调节系统和方法识别与第一阶段中的集成电路器件系列相关的特征数据，并且识别在第二阶段中候选集成电路器件的相关联的工艺分组。 然后使用来自第一阶段的表征数据来提供对应于候选设备的目标操作频率的电源电压。 另一方面，混合电压调节器电路包括开环电路，其自动识别集成电路器件的工艺分离，并且允许调节器基于该工艺分离特有的特性数据修改供电电压，以及闭环电路 调节电源电压。 在一个实施例中，闭环电路包括关键路径副本，用于提供集成电路设备中的关键路径所需的估计工作频率。 在一个实施例中，在关键路径和/或开环电路中可以使用环形振荡器电路。

公开(公告)号：US20070177419A1

公开(公告)日：2007-08-02

申请号：US11621679

申请日：2007-01-10

申请人： Manoj Sachdev ,  Mohammad Sharifkhani

发明人： Manoj Sachdev ,  Mohammad Sharifkhani

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

摘要翻译： 提供了非对称静态随机存取存储器（SRAM）单元。 SRAM单元包括第一和第二存储节点，驱动晶体管和存取晶体管。 第一和第二存储节点被配置为存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的高电压和低电压电源，并且通过反馈回路保持第一逻辑状态。 存取晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的第一和第二位线，并通过相对晶体管漏电流维持第二逻辑状态。 还提供了用于从SRAM单元读取和写入SRAM单元的方法。

公开(公告)号：US06445235B1

公开(公告)日：2002-09-03

申请号：US08498549

申请日：1995-07-05

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： H03K3356

CPC分类号： G06F11/2236 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/318541 ,  G01R31/318577

摘要： A flipflop has master and slave interconnected through a buffer. The master has its inverters located outside the signal path from input to output, as the buffer provides the driving capability required for both IDDQ-testing and operational use. This configuration enables IDDQ-testing without further circuitry added to the flipflop and reduces propagation delay in the signal path.

摘要翻译： 触发器具有通过缓冲器互连的主机和从机。 主器件的反相器位于从输入到输出的信号路径之外，因为缓冲器提供了IDDQ测试和操作使用所需的驱动能力。 这种配置可以进行IDDQ测试，而不需要将额外的电路添加到触发器，并减少信号路径中的传播延迟。

公开(公告)号：US06429711B1

公开(公告)日：2002-08-06

申请号：US09608314

申请日：2000-06-30

申请人： James W. Tschanz ,  Manoj Sachdev ,  Siva G. Narendra ,  Vivek K. De

发明人： James W. Tschanz ,  Manoj Sachdev ,  Siva G. Narendra ,  Vivek K. De

IPC分类号： H03K3356

CPC分类号： H03K3/356121 ,  H03K17/163

摘要： A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.

摘要翻译： 包括输入数据信号的数据信号的电路，输入时钟信号的时钟信号，产生控制时钟的时钟电路以及接收数据信号和控制时钟的多输入条件逆变器， 输出。 电路还包括耦合到多输入条件逆变器中的高信号传输节点的至少一个堆叠节点预充电晶体管和耦合到多输入条件逆变器中的低信号传输节点的至少一个堆叠节点预放电晶体管。 保持器电路接收多输入条件反相器的输出，缓冲电路接收多输入条件反相器的输出，并产生电路输出。

公开(公告)号：US10396796B2

公开(公告)日：2019-08-27

申请号：US15575197

申请日：2016-05-20

申请人： Nikolaos Papadopoulos ,  Manoj Sachdev ,  William Wong

发明人： Nikolaos Papadopoulos ,  Manoj Sachdev ,  William Wong

IPC分类号： H03K19/0944 ,  H03K19/094 ,  G09G3/20 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  G09G3/34 ,  H01L29/24

摘要： A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.

公开(公告)号：US07872938B2

公开(公告)日：2011-01-18

申请号：US12549757

申请日：2009-08-28

申请人： Manoj Sachdev ,  Shah M Jahinuzzaman

发明人： Manoj Sachdev ,  Shah M Jahinuzzaman

IPC分类号： G11C8/00

CPC分类号： G11C7/02 ,  G11C11/4125

摘要： A Static Random Access Memory (SRAM) cell storage configuration is described, having an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error.

摘要翻译： 描述了静态随机存取存储器（SRAM）单元存储配置，其对辐射诱导的软错误具有改进的鲁棒性。 SRAM单元存储配置包括以下元件。 配置第一和第二存储节点以存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。 负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。 至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈，冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。

公开(公告)号：US07372721B2

公开(公告)日：2008-05-13

申请号：US11552655

申请日：2006-10-25

申请人： Manoj Sachdev ,  Mohammad Sharifkhani

发明人： Manoj Sachdev ,  Mohammad Sharifkhani

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/12 ,  G11C11/412

摘要： A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.

摘要翻译： 提供了一种减少漏电流的静态随机存取存储器（SRAM）单元阵列。 SRAM单元阵列被配置成多列。 每列包括：虚拟虚拟接地节点; 用于选择性地将列虚拟接地节点耦合到接地或标称低电压之一的列开关; 和多个段。 每个段包括：段虚拟接地节点; 多个SRAM单元，包括耦合到所述段虚拟接地节点的虚拟接地信号; 以及用于选择性地将段虚拟接地节点耦合到标称低电压或列虚拟接地节点之一的虚拟接地开关。 还描述了用于操作SRAM单元阵列的方法。

公开(公告)号：US6127838A

公开(公告)日：2000-10-03

申请号：US33728

申请日：1998-03-03

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： H01L21/82 ,  G01R31/30 ,  G01R31/3185 ,  G11C29/00 ,  H03K19/00

CPC分类号： G01R31/3008 ,  G01R31/3004 ,  G01R31/318516

摘要： The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).

摘要翻译： 本发明涉及一种集成电路，其包括具有AND平面和OR平面的动态CMOS可编程逻辑阵列（PLA）。 本发明还涉及一种用于测试这种电路的方法。 根据本发明的PLA提供了能够检测桥接故障的装置。 相邻的线可以被驱动到互补的逻辑电平。 交叉晶体管可以关闭。 以这种方式，线路之间的桥接故障产生可观察到的提高的静态电源电流（IDDQ）。

公开(公告)号：US5969653A

公开(公告)日：1999-10-19

申请号：US951036

申请日：1997-10-15

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/108 ,  H03M1/12

摘要： The invention relates to an integrated circuit, containing an A/D converter and a test circuit, the latter in a test mode enabling explicit testing of analog and digital control signals of the circuit by supplying these control signals to circuit sections of the A/D converter and thus generating digital data signals at the output of the A/D converter. Analog signals, like bias signals and reference signals, can be selected and supplied to the input facility of the converter. Subsequently, a digital representation of the selected signal is obtained at the output facility of the converter. Digital signals, like clock signals, can be selected and supplied directly to the output facility. The output facility is operated by a clock signal and constructs a clocked version of the selected digital signal, which is subsequently available at the output. Thus, selected signals, either digital or analog, are available at the output of the converter and can be compared to specified data.

摘要翻译： 本发明涉及一种包含A / D转换器和测试电路的集成电路，后者采用测试模式，能够通过将这些控制信号提供给A / D的电路部分来显式测试电路的模拟和数字控制信号 转换器，从而在A / D转换器的输出端产生数字数据信号。 可以选择模拟信号，如偏置信号和参考信号，并将其提供给转换器的输入设备。 随后，在转换器的输出设备处获得所选信号的数字表示。 数字信号，如时钟信号，可以选择并直接提供给输出设备。 输出设备由时钟信号操作，并构建所选择的数字信号的时钟版本，随后在输出端可用。 因此，选择的数字或模拟信号在转换器的输出端可用，并且可以与指定的数据进行比较。

公开(公告)号：US5831986A

公开(公告)日：1998-11-03

申请号：US546856

申请日：1995-10-23

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： G11C11/413 ,  G11C8/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12

CPC分类号： G11C29/88 ,  G11C29/02 ,  G11C29/10

摘要： Hard-open defects between logic gates of an address decoder and the voltage supply render a memory conditionally inoperative. The decoders are therefore examined for such hard-open defects. Two cells of two logically adjacent rows or columns are written with complementary logic data. If a Read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect in the decoders is demonstrated. Alternatively, the memory is provided with a fault-tolerant decoder that comprises additional disabling circuitry to properly disable the rows and columns even when a hard-open defect is present in the decoders' logic gates.

摘要翻译： 地址解码器的逻辑门与电源之间的硬开缺陷使得存储器有条件地不起作用。 因此，检查解码器是否存在这样的硬开放缺陷。 两个逻辑相邻行或列的两个单元格用互补逻辑数据写入。 如果读取操作将两个单元格中的数据显示为相同，则说明解码器中硬开放缺陷的存在和位置。 或者，存储器被提供有容错解码器，其包括附加禁用电路，以便即使在解码器的逻辑门中存在硬开放缺陷，也适当地禁用行和列。