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    CONFIGURABLE MEMORY CONTROLLER
    11.
    发明申请
    CONFIGURABLE MEMORY CONTROLLER 审中-公开
    可配置内存控制器

    公开(公告)号：US20110276766A1

    公开(公告)日：2011-11-10

    申请号：US12774462

    申请日：2010-05-05

    Applicant: Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    Inventor： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    IPC: G06F12/00

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3215 ,  G06F13/1626 ,  H04W52/0274 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D70/142 ,  Y02D70/144

    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    Abstract translation: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。

    MODULAR INTEGRATED CIRCUIT WITH CLOCK CONTROL CIRCUIT
    12.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH CLOCK CONTROL CIRCUIT 有权
    具有时钟控制电路的模块化集成电路

    公开(公告)号：US20110264946A1

    公开(公告)日：2011-10-27

    申请号：US12767226

    申请日：2010-04-26

    Applicant: Greg Goodemote ,  Khan Kibria ,  Mark N. Fullerton ,  Niray P. Dagli ,  Liang Deng ,  Sam Liu

    Inventor： Greg Goodemote ,  Khan Kibria ,  Mark N. Fullerton ,  Niray P. Dagli ,  Liang Deng ,  Sam Liu

    IPC: G06F1/08

    CPC classification number: G06F1/26 ,  G06F1/06 ,  G06F1/08

    Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

    Abstract translation: 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块 接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

    Frequency-dependent voltage control in digital logic
    13.
    发明授权
    Frequency-dependent voltage control in digital logic 有权
    数字逻辑中的频率依赖电压控制

    公开(公告)号：US07603575B2

    公开(公告)日：2009-10-13

    申请号：US11173218

    申请日：2005-06-30

    Applicant: Nancy G. Woodbridge ,  Mark N. Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    Inventor： Nancy G. Woodbridge ,  Mark N. Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    IPC: G06F1/00 ,  G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

    Abstract translation: 电子电路包括至少一个数字逻辑电路; 和电源控制电路。 功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。 在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压 频率下降。

    Memory power manager
    17.
    发明授权
    Memory power manager 有权
    内存电源管理器

    公开(公告)号：US08812889B2

    公开(公告)日：2014-08-19

    申请号：US12774479

    申请日：2010-05-05

    Applicant: Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    Inventor： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    IPC: G06F1/26 ,  G06F1/32 ,  G06F13/16

    CPC classification number: G06F13/1668 ,  G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    Abstract translation: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。

    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING
    18.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING 审中-公开
    具有均匀地址映射的模块化集成电路

    公开(公告)号：US20130138936A1

    公开(公告)日：2013-05-30

    申请号：US13752961

    申请日：2013-01-29

    Applicant: Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    Inventor： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC: G06F9/00

    CPC classification number: G06F9/00 ,  G06F1/06 ,  G06F1/189 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

    Abstract translation: 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。

    MODULAR INTEGRATED CIRCUIT WITH COMMON SOFTWARE
    19.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH COMMON SOFTWARE 有权
    具有通用软件的模块化集成电路

    公开(公告)号：US20110264901A1

    公开(公告)日：2011-10-27

    申请号：US12767201

    申请日：2010-04-26

    Applicant: Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    Inventor： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC: G06F15/177 ,  G06F1/04 ,  G06F1/24 ,  G06F12/02

    CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

    Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.

    Abstract translation: 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 辐条模块包括多个具有硬件地址的接口电路。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件包括对应于多个接口电路的多个驱动器模块。 处理模块基于多个接口电路中的每一个的硬件地址执行引导固件以配置多个驱动器模块。

    Closed loop voltage control using adjustable delay lines
    20.
    发明授权
    Closed loop voltage control using adjustable delay lines 有权
    使用可调延迟线的闭环电压控制

    公开(公告)号：US08046601B1

    公开(公告)日：2011-10-25

    申请号：US11962071

    申请日：2007-12-20

    Applicant: Nir Paz ,  Mark N. Fullerton

    Inventor： Nir Paz ,  Mark N. Fullerton

    IPC: G06F1/00 ,  G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/32

    Abstract: Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.

    Abstract translation: 控制向集成电路的目标电路提供电压的电源。 由电源电压供电的可调延迟线与目标电路位于IC上。 可调延迟线经受与目标电路基本相同的操作条件。 控制单元测量可调延迟线的延迟时间。 基于测量的延迟时间，控制单元输出控制信号，通过该控制信号电源调节电源电压。 可调延迟线包括多个不同的延迟元件，每个延迟元件具有对操作条件变化的延迟特性和响应性。 每个延迟元件模拟目标电路中的物理元件（例如，门和线）的延迟特性。 以这种方式，可以在仍然保持目标电路的适当操作的同时降低功耗。

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