公开(公告)号：US4974226A

公开(公告)日：1990-11-27

申请号：US247288

申请日：1988-09-22

申请人： Kumiko Fujimori ,  Hirofumi Shinohara

发明人： Kumiko Fujimori ,  Hirofumi Shinohara

IPC分类号： G06F12/16 ,  G01R31/319 ,  G06F11/22 ,  G11C29/38 ,  G01R31/28

CPC分类号： G11C29/38 ,  G01R31/31917

摘要： Test data stored in a data register 13a are applied to a data generator 11a and compared with a 1 bit signal stored in a scan latch 1c to determine the coincidence or non-coincidence therebetween. Outputs from the data generator 11a are applied to RAM 10 to be written in a designated region in a memory cell array 6. Data read from the said region of the memory cell array 6 are compared with expected value data in a comparator 12. Thus, the collation of data is carried out.

摘要翻译： 将存储在数据寄存器13a中的测试数据应用于数据发生器11a，并与存储在扫描锁存器1c中的1位信号进行比较，以确定它们之间的一致或非重合。 来自数据发生器11a的输出被施加到RAM10以写入存储单元阵列6中的指定区域。从存储单元阵列6的所述区域读取的数据与比较器12中的期望值数据进行比较。因此， 进行数据整理。

公开(公告)号：US20110273952A1

公开(公告)日：2011-11-10

申请号：US13186769

申请日：2011-07-20

申请人： Koji NII ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

发明人： Koji NII ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/063 ,  G11C11/412

摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US06864548B2

公开(公告)日：2005-03-08

申请号：US10167655

申请日：2002-06-13

申请人： Hirofumi Shinohara ,  Tomohiro Ushio

发明人： Hirofumi Shinohara ,  Tomohiro Ushio

IPC分类号： H01L21/82 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC分类号： H01L27/1126 ,  G11C17/12 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, wherein the lowering, in comparison with a background art, of the resistance of a source line is achieved and a manufacturing method for the same are obtained.A protruding portion (2m) that protrudes in the Y direction towards each drain region (3m) from a trunk portion (1) is formed in a source line (SLa) in each of five memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the m-th row. In the same manner, a protruding portion (2n) that protrudes in the Y direction towards each drain region (3n) from the trunk portion (1) is formed in the source line (SLa) in each of four memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the n-th row.

摘要翻译： 一种半导体器件，其中与背景技术相比，实现了源极线的电阻的降低，并且获得了一种用于其的制造方法。一种在Y方向上朝向每个漏极区域突出的突出部分（2m） 在从属于第m行的8个存储单元中的ROM代码的“1”的5个存储单元的每一个的源极线（SLa）中形成有来自主干部分（1）的（3m）。 以相同的方式，在与“1”对应的四个存储单元中的每一个中，在源极线（SLa）中形成从主体部分（1）向Y方向朝向每个漏极区域（3n）突出的突出部分（2n） “来自属于第n行的8个存储单元中的ROM代码。

公开(公告)号：US5444822A

公开(公告)日：1995-08-22

申请号：US77143

申请日：1993-06-16

申请人： Hirofumi Shinohara

发明人： Hirofumi Shinohara

IPC分类号： G06F15/18 ,  G06G7/60 ,  G06N3/063 ,  G06N99/00

CPC分类号： G06N3/063

摘要： A semiconductor integrated circuit device electrically simulating a vital neural network includes neuron units. Each neuron unit includes a plurality of laterally connected synapse units, an accumulator for accumulatively adding the outputs of the final synapse unit in the lateral connection, and a nonlinear processor for carrying out a predetermined nonlinear operational processing on the output of the accumulator. The number of the neuron units and the number of synapse units per neuron unit satisfy a relation of an integer multiple. The number of regularly operating neuron units can be made equal to that of the synapse units per neuron unit, whereby it is possible to prevent the neuron units from performing meaningless operations and an efficient neural network can be obtained.

摘要翻译： 电动模拟重要神经网络的半导体集成电路装置包括神经元单元。 每个神经元单元包括多个横向连接的突触单元，用于在侧向连接中累积地添加最终突触单元的输出的累加器，以及用于对累加器的输出执行预定非线性运算处理的非线性处理器。 神经元单位的数量和每个神经元单元的突触单元数量满足整数倍的关系。 可以使经常运行的神经元单位的数量等于每个神经元单位的突触单位的数量，由此可以防止神经元单元执行无意义的操作，并且可以获得有效的神经网络。

公开(公告)号：US5383132A

公开(公告)日：1995-01-17

申请号：US894663

申请日：1992-06-05

申请人： Hirofumi Shinohara ,  Yoshiki Tsujihashi ,  Hisashi Matsumoto

发明人： Hirofumi Shinohara ,  Yoshiki Tsujihashi ,  Hisashi Matsumoto

IPC分类号： G01N21/88 ,  G01N21/93 ,  G01N21/956 ,  G06F17/50 ,  H01L21/66 ,  H01L21/82 ,  G06F15/60 ,  G06F15/40

CPC分类号： G06F17/5081

摘要： A design verification device includes a diagram data memory for storing designed diagram data, a design reference value memory for storing a design reference value, a determination circuit for making determination with different weight between intersecting directions of a diagram to either the distance or the design reference value in calculating the distance between diagram data provided from the diagram data memory means for making determination whether the calculated distance follows the design reference value; and an error signal output circuit for providing an error signal when determination is made that the design reference value is not followed by the determination circuit.

摘要翻译： 设计验证装置包括用于存储设计图表数据的图形数据存储器，用于存储设计参考值的设计参考值存储器，用于在图的相交方向与距离或设计参考值的相交方向之间进行不同重量的确定的确定电路 计算从图形数据存储装置提供的图形数据之间的距离的值，用于确定所计算的距离是否遵循设计参考值; 以及误差信号输出电路，用于当确定设计参考值未被确定电路跟随时提供误差信号。

公开(公告)号：US4954992A

公开(公告)日：1990-09-04

申请号：US269757

申请日：1988-11-08

申请人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

发明人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G11C7/1057 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/062 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

摘要翻译： 一种动态随机存取存储器件包括一对写入数据传送总线，用于传送要被写入的数据，一对读出数据传输总线，用于传送要被读取的数据，附加地和独立于写入数据传输总线 对和由CMOS晶体管形成的多个电流镜型读出放大器，并且每个放大器设置在位线对和读出数据传输总线对之间，并且具有连接到相应位线对和读出数据的输入节点 传输总线对形成其输出节点。 响应于比传统的触发器型读出放大器被激活的时间早的列解码器的输出，CMOS晶体管的电流镜式读出放大器被激活。

公开(公告)号：US4751683A

公开(公告)日：1988-06-14

申请号：US771709

申请日：1985-09-03

申请人： Tomohisa Wada ,  Hirofumi Shinohara

发明人： Tomohisa Wada ,  Hirofumi Shinohara

IPC分类号： G11C11/34 ,  G11C8/08 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C8/18

摘要： A semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.

摘要翻译： 根据本发明的半导体存储器件响应于用于检测x地址变化的地址转换检测（ATD）信号以及写入使能信号和上拉沿W而在所选择的字线上产生信号电平 根据读取模式和写入模式而变化，从而可以减少功率耗散。

公开(公告)号：US08414231B2

公开(公告)日：2013-04-09

申请号：US13368484

申请日：2012-02-08

申请人： Kouichi Katoh ,  Takamasa Itoh ,  Yoshiaki Mikami ,  Norihiro Miyazawa ,  Hirofumi Shinohara

发明人： Kouichi Katoh ,  Takamasa Itoh ,  Yoshiaki Mikami ,  Norihiro Miyazawa ,  Hirofumi Shinohara

IPC分类号： B23C3/00 ,  B23C3/12

CPC分类号： B23C3/00 ,  B23C2220/56 ,  G05B19/4097 ,  Y10T409/300896 ,  Y10T409/303808 ,  Y10T409/304144 ,  Y10T409/307056 ,  Y10T409/308288 ,  Y10T409/30868 ,  Y10T483/1795

摘要： A machining method of a press die having a pierce cutter and a secondary relief-clearance area recessed inward relative to a profile of the pierce cutter. A plunge cutting tool has an edge portion protruding from an outer circumference of a tool body and can carve while rotating and moving in an axial direction of the tool body. While rotating the plunge cutting tool with an axis of the tool body being approximately parallel to a surface of the pierce cutter, the plunge cutting tool is relatively moved along the profile of the pierce cutter. The plunge cutting tool is also relatively moved in the axial direction of the tool body along the shape of the pierce cutter and the secondary relief-clearance area in a piercing direction each time the plunge cutting tool is relatively moved by a predetermined pitch.

摘要翻译： 一种具有穿孔切割器和相对于穿孔切割器的轮廓向内凹入的次级释放间隙区域的压模的加工方法。 插入式切削工具具有从工具主体的外周突出的边缘部，并且能够沿着工具主体的轴向旋转并移动而进行雕刻。 当刀具本体的轴线大致平行于穿孔刀的表面旋转插入式切割工具时，插入式切割工具沿着穿孔刀的轮廓相对移动。 每当插入式切削工具以预定的间距相对移动时，插入式切削工具也沿着穿孔刀具的形状沿着穿孔方向相对移动，并且在穿孔方向上相对移动。

公开(公告)号：US07683155B2

公开(公告)日：2010-03-23

申请号：US10524636

申请日：2003-08-29

申请人： Shigeki Inatomi ,  Noboru Tanoue ,  Motoji Yokoyama ,  Hirofumi Shinohara ,  Satoshi Takehara

发明人： Shigeki Inatomi ,  Noboru Tanoue ,  Motoji Yokoyama ,  Hirofumi Shinohara ,  Satoshi Takehara

IPC分类号： C08G8/02 ,  C08G8/04 ,  C08G14/02

CPC分类号： C08G8/04 ,  C08G8/28

摘要： A phenolic novolak having the contents of a monomeric phenol and a dimeric phenol and a degree of dispersion controlled can be obtained in high yield by a process for production of a phenolic novolak having a step of conducting a heterogeneous reaction of a phenol and an aldehyde in the presence of a phosphoric acid and an unreactive oxygen-containing organic solvent as a reaction cosolvent.

摘要翻译： 通过具有进行苯酚和醛的非均相反应的酚醛清漆的制造方法，可以高收率地获得具有单体苯酚和二聚苯酚含量的苯酚酚醛清漆和分散度控制的酚醛清漆 存在磷酸和不含活性的含氧有机溶剂作为反应助溶剂。

公开(公告)号：US20090133461A1

公开(公告)日：2009-05-28

申请号：US12276441

申请日：2008-11-24

申请人： KOUICHI KATOH ,  Takamasa Itoh ,  Yoshiaki Mikami ,  Norihiro Miyazawa ,  Hirofumi Shinohara

发明人： KOUICHI KATOH ,  Takamasa Itoh ,  Yoshiaki Mikami ,  Norihiro Miyazawa ,  Hirofumi Shinohara

IPC分类号： B21D37/00 ,  B21D28/00 ,  B23C3/00 ,  G05B19/4097

CPC分类号： B23C3/00 ,  B23C2220/56 ,  G05B19/4097 ,  Y10T409/300896 ,  Y10T409/303808 ,  Y10T409/304144 ,  Y10T409/307056 ,  Y10T409/308288 ,  Y10T409/30868 ,  Y10T483/1795

摘要： A machining method of a press die having a pierce cutter and a secondary relief-clearance area recessed inward relative to a profile of the pierce cutter is provided. A plunge cutting tool having a tool body and at least one edge portion provided on an outer circumference of an end of the tool body is used, the edge portion being protruding from the outer circumference of the tool body and being capable of carving while rotating around an axis of the tool body and moving in an axial direction of the tool body. While rotating the plunge cutting tool with an axis of the tool body being approximately parallel to a surface of the pierce cutter, the plunge cutting tool is relatively moved along the profile of the pierce cutter. The plunge cutting tool is also relatively moved in the axial direction of the tool body along the shape of the pierce cutter and the secondary relief-clearance area in a piercing direction each time the plunge cutting tool is relatively moved by a predetermined pitch.

摘要翻译： 提供了一种具有穿孔切割器和相对于穿孔刀的轮廓向内凹入的副卸压间隙区域的冲压模具的加工方法。 使用具有工具主体和设置在工具主体的端部的外周上的至少一个边缘部分的插入切削工具，该边缘部分从工具主体的外周突出并且能够在旋转周围进行雕刻 工具主体的轴线并沿着工具主体的轴向方向移动。 当刀具本体的轴线大致平行于穿孔刀的表面旋转插入式切割工具时，插入式切割工具沿着穿孔刀的轮廓相对移动。 每当插入式切削工具以预定的间距相对移动时，插入式切削工具也沿着穿孔刀具的形状沿着穿孔方向相对移动，并且在穿孔方向上相对移动。