公开(公告)号：US5138412A

公开(公告)日：1992-08-11

申请号：US636556

申请日：1991-01-07

申请人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A dynamic RAM comprises a semiconductor substrate, first and second MOS transistor formed on said semiconductor substrate, each having a source, a drain, and a gate, a first insulation film formed on said first and second MOS transistors, a first electrode formed on said first insulation film, for accumulating an electrical charge, the first electrode extending through a first hole made in the first insulation film and connected to one of the source and drain of said first MOS transistor, a second electrode formed on the first insulation film, for accumulating an electrical charge, the second electrode extending through a second hole made in the first insulation film and connected to one of the source and drain of the second MOS transistor, and at least one part of the second electrode being spaced apart from, located above, and overlapping part of the first electrode, first and second capacitor-insulating films formed on the first and second electrodes, respectively, and a capacitor electrode fromed on the first and second capacitor-insulating films and having a portion interposed between the overlapping parts of the first and second electrodes.

摘要翻译： 动态RAM包括形成在所述半导体衬底上的半导体衬底，每个具有源极，漏极和栅极的第一和第二MOS晶体管，形成在所述第一和第二MOS晶体管上的第一绝缘膜，形成在所述第一和第二MOS晶体管上的第一电极， 第一绝缘膜，用于累积电荷，所述第一电极延伸穿过由所述第一绝缘膜制成的第一孔并连接到所述第一MOS晶体管的源极和漏极中的一个，形成在所述第一绝缘膜上的第二电极，用于 累积电荷，所述第二电极延伸通过在所述第一绝缘膜中制成的第二孔并且连接到所述第二MOS晶体管的源极和漏极中的一个，并且所述第二电极的至少一部分与所述第二绝缘膜上的 以及分别形成在第一和第二电极上的第一电极，第一和第二电容器绝缘膜的重叠部分，以及电容器e 在第一和第二电容器绝缘膜上引导，并且具有插入在第一和第二电极的重叠部分之间的部分。

公开(公告)号：US5106774A

公开(公告)日：1992-04-21

申请号：US650992

申请日：1991-02-04

申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.

摘要翻译： 公开了一种动态随机存取存储器，其包括具有形成在半导体衬底中的晶体管的沟槽型存储单元和布置在形成在衬底中并具有沟槽结构的沟槽中的电容器。 电容器包括形成在衬底上的杂质掺杂半导体层，以围绕沟槽并且具有与衬底的导电类型相反的导电类型，形成在沟槽中的第一电容器电极和具有绝缘层叠的部分的第二电容器电极 所述第一电容器电极在沟槽中。

公开(公告)号：US5998821A

公开(公告)日：1999-12-07

申请号：US859851

申请日：1997-05-21

申请人： Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10861 ,  H01L29/945

摘要： A dynamic RAM structure comprises a trench formed on a p-type Si substrate, a capacitor oxide film formed in such a manner as to cover an inner wall of the trench, a polysilicon film being a capacitor storage node electrode for burying the trench covered with the capacitor oxide film, an epitaxial Si layer formed on the Si substrate including an upper portion of the polysilicon film, a source/drain layer of a MOS transistor formed in the epitaxial Si layer, and a surface strap diffusion layer formed in the epitaxial Si layer in such a manner as to come in contact with the source/drain layer.

摘要翻译： 动态RAM结构包括形成在p型Si衬底上的沟槽，以覆盖沟槽内壁的方式形成的电容器氧化膜;多晶硅膜，其是用于埋入覆盖有沟槽的沟槽的电容器存储节点电极 电容器氧化膜，形成在包括多晶硅膜的上部的Si衬底上的外延Si层，形成在外延Si层中的MOS晶体管的源极/漏极层和形成在外延Si中的表面带扩散层 以与源极/漏极层接触的方式。

公开(公告)号：US5119155A

公开(公告)日：1992-06-02

申请号：US619616

申请日：1990-11-29

申请人： Katsuhiko Hieda ,  Tohru Ozaki

发明人： Katsuhiko Hieda ,  Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： In a semiconductor memory device, a trench is formed in a surface of a memory cell forming region of the substrate. The overall surface of the memory cell forming region, inclusive of the inner wall of the trench, is covered with an insulator film. A capacitor is formed on the inner surface of the trench through the insulator film. A MOSFET is formed in a semiconductor layer formed on a surface of a flat portion of the substrate. One of the source and drain regions of the MOSFET reaches the periphery of the trench so as to be connected to a storage node electrode of the capacitor.

摘要翻译： 在半导体存储器件中，在衬底的存储单元形成区域的表面上形成沟槽。 存储单元形成区域的整个表面（包括沟槽的内壁）被绝缘膜覆盖。 通过绝缘膜在沟槽的内表面上形成电容器。 MOSFET形成在形成在基板的平坦部分的表面上的半导体层中。 MOSFET的源极和漏极区域之一到达沟槽的周边，以便连接到电容器的存储节点电极。

公开(公告)号：US5371024A

公开(公告)日：1994-12-06

申请号：US947907

申请日：1992-09-21

申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Hiroshi Takato ,  Fujio Masuoka

发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Hiroshi Takato ,  Fujio Masuoka

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7834 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621

摘要： A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.

摘要翻译： 半导体器件具有第一导电类型的半导体衬底，掩埋在形成于衬底的元件区域中的沟槽中的栅电极，第二导电类型的第一源极和漏极区域形成在两侧的半导体衬底的表面区域中 的栅极电极，以及第二源极和漏极区域，其浓度高于第一源极和漏极区域的浓度，第二源极和漏极区域形成在栅极的任一侧上的半导体衬底的表面区域中 电极，与栅极间隔开，并分别与第一源极和漏极区相邻。 该半导体器件具有其中栅极深埋在衬底中的结构。 因此，可以防止短的通道效应。 埋在沟槽中的栅电极延伸穿过在半导体衬底的表面区域中形成的具有低杂质浓度的半导体区域，因此形成两个低杂质浓度区域。 源区和漏区分别由低杂质浓度区和与其相邻的高杂质浓度区组成。 低杂质浓度区域可显着提高漏极击穿电压。

公开(公告)号：US5736760A

公开(公告)日：1998-04-07

申请号：US632321

申请日：1996-04-15

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

公开(公告)号：US5508541A

公开(公告)日：1996-04-16

申请号：US124300

申请日：1993-09-20

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

摘要翻译： MOS随机存取存储器件包括其中形成有沟槽的半导体衬底和衬底上的存储器单元的阵列。 每个存储单元包括1位数据存储电容器和转移栅极MOS晶体管。 电容器包括埋在沟槽中的绝缘层，其用作存储节点。 岛状半导体层至少部分地覆盖基板上的存储节点层，并且与其耦合。 晶体管具有源极和漏极，在衬底中限定其间的沟道区域，以及覆盖沟道区域的绝缘栅极。 源极和漏极中的一个直接耦合到岛状层，而另一个与与其相关联的相应数据传输线（位线）接触。

公开(公告)号：US07759174B2

公开(公告)日：2010-07-20

申请号：US11657088

申请日：2007-01-24

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/66825 ,  Y10S257/905

摘要： A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.

摘要翻译： 半导体器件包括：衬底，其包括半导体和沟槽;以及在该衬底上的电可重写半导体存储单元，所述半导体存储单元包括电荷存储层，所述电荷存储层包括上表面和下表面，所述下表面的面积较小 比电荷存储层的下表面和沟槽的底面之间的第一绝缘层设置在沟槽中的电荷存储层的至少一部分，第二绝缘层在侧面 沟槽的表面和电荷存储层的侧表面和沟槽的侧表面与第一绝缘层的侧表面之间，电荷存储层上的第三绝缘层和第三绝缘层上的控制栅极电极 。

公开(公告)号：US07071107B2

公开(公告)日：2006-07-04

申请号：US10674382

申请日：2003-10-01

申请人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

发明人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

IPC分类号： H01L21/302

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31683 ,  H01L21/76224 ,  H01L21/76229

摘要： There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

摘要翻译： 公开了一种制造半导体器件的方法，其中在硅衬底的表面上形成Si 3 N 4 N 4膜作为掩模构件，然后蚀刻形成 一个STI沟槽。 将过氢化硅氮烷聚合物的溶液涂布在其上形成有STI沟槽的硅衬底的表面上，以在其上沉积涂膜（PSZ膜）。 去除沉积在掩模构件上的PSZ膜，使PSZ膜的一部分留在沟槽内，其中控制PSZ膜的厚度使其从STI沟槽底部的高度变为600nm以下。 然后，在含水蒸汽的气氛中对PSZ膜进行热处理，通过PSZ膜的化学反应将PSZ膜转换为氧化硅膜。 随后，对氧化硅膜进行热处理以使氧化硅膜致密化。

公开(公告)号：US06992358B2

公开(公告)日：2006-01-31

申请号：US10874732

申请日：2004-06-24

申请人： Katsuhiko Hieda ,  Kazuya Matsuzawa ,  Daisuke Hagishima

发明人： Katsuhiko Hieda ,  Kazuya Matsuzawa ,  Daisuke Hagishima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78648

摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

摘要翻译： 公开了一种半导体器件，包括具有凹陷的基底绝缘膜，半导体结构，其包括具有形成在下面的绝缘膜上的部分的第一半导体部分和与凹部重叠的第一重叠部分，第二半导体部分形成有部分 在第一半导体部分和第二半导体部分之间并且具有设置在该凹部之上的部分的第三半导体部分，其中第一重叠部分的重叠宽度和第二重叠部分的重叠宽度 第二重叠部分彼此相等，栅电极包括覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹陷部中的第二电极部分，以及插入在半导体结构和栅极之间的栅极绝缘膜 电极。