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    Method of making dynamic random access semiconductor memory device
    5.
    发明授权
    Method of making dynamic random access semiconductor memory device 失效
    制作动态随机存取半导体存储器件的方法

    公开(公告)号：US5350708A

    公开(公告)日：1994-09-27

    申请号：US77744

    申请日：1993-06-18

    申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10841 ,  H01L27/10823

    摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

    摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的

    Dynamic ram, having an improved large capacitance
    6.
    发明授权
    Dynamic ram, having an improved large capacitance 失效
    动态ram，具有改进的大电容

    公开(公告)号：US5138412A

    公开(公告)日：1992-08-11

    申请号：US636556

    申请日：1991-01-07

    申请人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    发明人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： A dynamic RAM comprises a semiconductor substrate, first and second MOS transistor formed on said semiconductor substrate, each having a source, a drain, and a gate, a first insulation film formed on said first and second MOS transistors, a first electrode formed on said first insulation film, for accumulating an electrical charge, the first electrode extending through a first hole made in the first insulation film and connected to one of the source and drain of said first MOS transistor, a second electrode formed on the first insulation film, for accumulating an electrical charge, the second electrode extending through a second hole made in the first insulation film and connected to one of the source and drain of the second MOS transistor, and at least one part of the second electrode being spaced apart from, located above, and overlapping part of the first electrode, first and second capacitor-insulating films formed on the first and second electrodes, respectively, and a capacitor electrode fromed on the first and second capacitor-insulating films and having a portion interposed between the overlapping parts of the first and second electrodes.

    摘要翻译： 动态RAM包括形成在所述半导体衬底上的半导体衬底，每个具有源极，漏极和栅极的第一和第二MOS晶体管，形成在所述第一和第二MOS晶体管上的第一绝缘膜，形成在所述第一和第二MOS晶体管上的第一电极， 第一绝缘膜，用于累积电荷，所述第一电极延伸穿过由所述第一绝缘膜制成的第一孔并连接到所述第一MOS晶体管的源极和漏极中的一个，形成在所述第一绝缘膜上的第二电极，用于 累积电荷，所述第二电极延伸通过在所述第一绝缘膜中制成的第二孔并且连接到所述第二MOS晶体管的源极和漏极中的一个，并且所述第二电极的至少一部分与所述第二绝缘膜上的 以及分别形成在第一和第二电极上的第一电极，第一和第二电容器绝缘膜的重叠部分，以及电容器e 在第一和第二电容器绝缘膜上引导，并且具有插入在第一和第二电极的重叠部分之间的部分。

    Dynamic type semiconductor memory device and its manufacturing method
    7.
    发明授权
    Dynamic type semiconductor memory device and its manufacturing method 失效
    动态型半导体存储器件及其制造方法

    公开(公告)号：US5250830A

    公开(公告)日：1993-10-05

    申请号：US797192

    申请日：1991-11-25

    申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

    CPC分类号： H01L27/10841 ,  H01L27/10823

    摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

    摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的

    Semiconductor device and process for manufacturing the same
    8.
    发明授权
    Semiconductor device and process for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5371024A

    公开(公告)日：1994-12-06

    申请号：US947907

    申请日：1992-09-21

    申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Hiroshi Takato ,  Fujio Masuoka

    发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Hiroshi Takato ,  Fujio Masuoka

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/7834 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621

    摘要： A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.

    摘要翻译： 半导体器件具有第一导电类型的半导体衬底，掩埋在形成于衬底的元件区域中的沟槽中的栅电极，第二导电类型的第一源极和漏极区域形成在两侧的半导体衬底的表面区域中 的栅极电极，以及第二源极和漏极区域，其浓度高于第一源极和漏极区域的浓度，第二源极和漏极区域形成在栅极的任一侧上的半导体衬底的表面区域中 电极，与栅极间隔开，并分别与第一源极和漏极区相邻。 该半导体器件具有其中栅极深埋在衬底中的结构。 因此，可以防止短的通道效应。 埋在沟槽中的栅电极延伸穿过在半导体衬底的表面区域中形成的具有低杂质浓度的半导体区域，因此形成两个低杂质浓度区域。 源区和漏区分别由低杂质浓度区和与其相邻的高杂质浓度区组成。 低杂质浓度区域可显着提高漏极击穿电压。

    Semiconductor memory with pad electrode and bit line under stacked capacitor
    9.
    发明授权
    Semiconductor memory with pad electrode and bit line under stacked capacitor 失效
    具有焊盘电极的半导体存储器和堆叠电容器下的位线

    公开(公告)号：US5235199A

    公开(公告)日：1993-08-10

    申请号：US831657

    申请日：1992-02-07

    申请人： Takeshi Hamamoto ,  Fumio Horiguchi ,  Katsuhiko Hieda

    发明人： Takeshi Hamamoto ,  Fumio Horiguchi ,  Katsuhiko Hieda

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10808 ,  Y10S257/905 ,  Y10S257/908

    摘要： A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.

    摘要翻译： 半导体存储器具有许多存储单元，每个存储单元都包括晶体管和电容器 在每个存储单元中，晶体管的源区和漏区中的一个连接到位线。 位线形成在晶体管的上方。 电容器包括形成在基板上的第一电容器电极和形成在涂覆在第一电容器电极的表面上的绝缘膜上的第二电容器电极。 第一电容器电极连接到晶体管的源极和漏极区域中的另一个。 第一电容器电极形成在位线上方。 为了制造这样的半导体存储器，每个存储单元区域分别形成在基板的表面上。 在存储单元区域上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 栅电极用作掩模以掺杂杂质以形成晶体管的源极和漏极区域。 位线形成并连接到源区和漏区之一。 第一电容器电极形成在位线上方并连接到源极和漏极区域中的另一个。 在第一电容器电极的表面上形成绝缘膜，在绝缘膜上形成第二电容电极。

    Semiconductor memory with insulation film embedded in groove formed on substrate
    10.
    发明授权
    Semiconductor memory with insulation film embedded in groove formed on substrate 失效
    具有绝缘膜的半导体存储器嵌入在衬底上形成的凹槽中

    公开(公告)号：US5561311A

    公开(公告)日：1996-10-01

    申请号：US350113

    申请日：1994-11-29

    申请人： Takeshi Hamamoto ,  Fumio Horiguchi ,  Katsuhiko Hieda

    发明人： Takeshi Hamamoto ,  Fumio Horiguchi ,  Katsuhiko Hieda

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10808 ,  Y10S257/905 ,  Y10S257/908

    摘要： A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line. A first capacitor electrode is formed on the first insulating film, making electrical contact with the other of the source and drain regions of the memory cell through a contact hole opened through the first insulating film and insulated from the bit line by the first insulating film. A second capacitor electrode is formed on the first capacitor electrode with a second insulating film provided therebetween. The insulation film is embedded in a groove formed on the semiconductor substrate.

    摘要翻译： 具有存储单元的半导体存储器形成在半导体衬底上。 每个存储单元都具有晶体管和电容器。 晶体管包括沟道区域，漏极区域和源极区域，其在一条直线上排列并且被来自相邻单元格的绝缘膜绝缘。 每个存储单元具有形成在沟道区上的栅电极，其间具有栅极绝缘膜。 焊盘电极与存储单元的源区和漏区之一电接触并在绝缘膜上延伸。 位线与上面的焊盘电极电接触，平行于线延伸并且与源区和漏区之一横向隔离。 在位线上的半导体衬底上形成第一绝缘膜。 第一电容器电极形成在第一绝缘膜上，通过穿过第一绝缘膜打开的接触孔与第一绝缘膜与位线绝缘而与存储单元的另一个源极和漏极区域电接触。 在第一电容器电极上形成第二电容器电极，其间设置有第二绝缘膜。 绝缘膜嵌入形成在半导体衬底上的沟槽中。