公开(公告)号：US5106774A

公开(公告)日：1992-04-21

申请号：US650992

申请日：1991-02-04

申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.

摘要翻译： 公开了一种动态随机存取存储器，其包括具有形成在半导体衬底中的晶体管的沟槽型存储单元和布置在形成在衬底中并具有沟槽结构的沟槽中的电容器。 电容器包括形成在衬底上的杂质掺杂半导体层，以围绕沟槽并且具有与衬底的导电类型相反的导电类型，形成在沟槽中的第一电容器电极和具有绝缘层叠的部分的第二电容器电极 所述第一电容器电极在沟槽中。

公开(公告)号：US4505025A

公开(公告)日：1985-03-19

申请号：US497407

申请日：1983-05-23

申请人： Kei Kurosawa ,  Fumio Horiguchi

发明人： Kei Kurosawa ,  Fumio Horiguchi

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762 ,  H01L21/95

CPC分类号： H01L21/31055 ,  H01L21/76 ,  H01L21/76229

摘要： A method for manufacturing a semiconductor device is disclosed which comprises the step of forming one or more first grooves by selectively etching a field region of a semiconductor substrate, the step of forming, on the entire surface of the substrate including the first groove, a first insulating film having a thickness substantially equal to or greater than the depth of the first groove, this first insulating film having on its upper surface one or more second grooves corresponding to the first groove, at least one of the second grooves having a width greater than its depth, the step of selectively forming, in at least one of the second grooves having a width greater than its depth, a second insulating film having a thickness substantially equal to the depth of the second groove, the step of forming a third insulating film having a flat surface on its whole surface, the step of applying an anisotropic dry etching technique to the resultant structure to expose the surface of the substrate, thereby obtaining a substrate which has a flat surface and having the first insulating material buried in the field region, and the step of forming a semiconductor element in the surface region of the substrate isolated by the first insulating material buried in the field region of the substrate.

摘要翻译： 公开了一种制造半导体器件的方法，其包括通过选择性地蚀刻半导体衬底的场区而形成一​​个或多个第一凹槽的步骤，在包括第一凹槽的衬底的整个表面上形成第一凹槽的步骤 绝缘膜的厚度基本上等于或大于第一凹槽的深度，该第一绝缘膜在其上表面上具有与第一凹槽对应的一个或多个第二凹槽，至少一个第二凹槽的宽度大于 其深度，在至少一个第二凹槽中选择性地形成具有大于其深度的宽度的步骤，具有基本上等于第二凹槽的深度的厚度的第二绝缘膜，形成第三绝缘膜的步骤 在其整个表面上具有平坦表面，对所得结构施加各向异性干法蚀刻技术以暴露该表面的步骤 从而获得具有平坦表面并且具有掩埋在场区域中的第一绝缘材料的衬底，以及在被掩埋在场区域中的第一绝缘材料隔离的衬底的表面区域中形成半导体元件的步骤 底物。

公开(公告)号：US4371407A

公开(公告)日：1983-02-01

申请号：US315909

申请日：1981-10-28

申请人： Kei Kurosawa

发明人： Kei Kurosawa

IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/312 ,  H01L7/44 ,  C23C15/00

CPC分类号： H01L21/0272 ,  H01L21/0271 ,  H01L21/2652

摘要： A method for producing a semiconductor device comprises the steps of:forming a first material film on a semiconductor substrate;forming a second material film on said first material film;selectively removing said second material film;exposing a structure thus formed to a gas plasma atmosphere to form a plasma polymerization film on at least an exposed surface of said first material film;removing a remainder of said second material film; andremoving the exposed surface of said first material film by using said plasma polymerization film as a mask to form a first material film pattern.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一材料膜; 在所述第一材料膜上形成第二材料膜; 选择性地去除所述第二材料膜; 将由此形成的结构暴露于气体等离子体气氛中，以在至少所述第一材料膜的暴露表面上形成等离子体聚合膜; 去除所述第二材料膜的剩余部分; 以及通过使用所述等离子体聚合膜作为掩模去除所述第一材料膜的暴露表面以形成第一材料膜图案。

公开(公告)号：US4951175A

公开(公告)日：1990-08-21

申请号：US353765

申请日：1989-05-18

申请人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

发明人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

IPC分类号： H01L27/108

CPC分类号： H01L27/10808 ,  H01L27/10835

摘要： A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

摘要翻译： 公开了一种具有层叠电容器单元结构的动态随机存取存储器，其具有设置在硅衬底上并具有MOSFET和电容器的存储单元。 在基板上形成绝缘层，在该绝缘层上形成第一多晶硅层。 这些层同时进行蚀刻并限定穿透它们的接触孔以与源的表面接触。 在第一多晶硅层上形成第二多晶硅层，以均匀地覆盖接触孔的内壁和通过接触孔露出的源的表面部分。 第一和第二硅层同时进行图案化以提供电容器的下电极。 在第二多晶硅层上形成电容器绝缘层之后，在电容器绝缘层上形成第三多晶硅层，从而埋入第二多晶硅层的凹部。 第三硅层构成电容器的上电极。

公开(公告)号：US4504333A

公开(公告)日：1985-03-12

申请号：US384946

申请日：1982-06-04

申请人： Kei Kurosawa

发明人： Kei Kurosawa

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762 ,  H01L21/22

CPC分类号： H01L21/31051 ,  H01L21/76 ,  H01L21/76224

摘要： A semiconductor device wherein an oxide film constituting a field region is buried in a semiconductor substrate to make the surface of the field region flush with the top surface of an element region, which is characterized in that another insulating film is buried between the oxide film and the element region. Said another insulating film allows the formation of a larger contact hole.A method for manufacturing such a semiconductor device which is characterized in making use of V-grooves formed in a lift-off process.

摘要翻译： 一种半导体器件，其中构成场区的氧化物膜被掩埋在半导体衬底中，以使场区的表面与元件区的顶表面齐平，其特征在于，另一绝缘膜被掩埋在氧化膜和 元素区域。 所述另一绝缘膜允许形成更大的接触孔。 一种制造这种半导体器件的方法，其特征在于利用在剥离过程中形成的V形槽。

公开(公告)号：US4407851A

公开(公告)日：1983-10-04

申请号：US335714

申请日：1981-12-29

申请人： Kei Kurosawa ,  Tadashi Shibata

发明人： Kei Kurosawa ,  Tadashi Shibata

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/31055

摘要： A method of forming a flat field region in a semiconductor substrate, which comprises forming a recess in the substrate, forming a covering on the whole surface of the substrate with a first insulating film such as plasma CVD SiO.sub.2 film which gives a layer at the side portion of the recess more rapidly etchable as compared with other portions, selectively removing the layer at the side portion to thereby form a V-shaped groove between the side of the recess and the first insulating film, and filling the V-shaped groove with a second insulating material so as to obtain a flat field region which is flush with the surface of an element-forming re

摘要翻译： 一种在半导体衬底中形成平坦场区的方法，包括在衬底中形成凹陷，在衬底的整个表面上用诸如等离子体CVD SiO 2膜的第一绝缘膜在侧面形成一层，形成覆盖层 与其他部分相比，凹部的更多部分可以更快速地蚀刻，在侧面选择性地去除层

公开(公告)号：US4874719A

公开(公告)日：1989-10-17

申请号：US221008

申请日：1988-07-18

申请人： Kei Kurosawa

发明人： Kei Kurosawa

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76877 ,  Y10S148/02 ,  Y10S148/026

摘要： Disclosed is a method for making connection between conductor layers through a contact via comprising the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming an insulation interlayer so that it covers the first conductive pattern, (c) forming, on the insulation interlayer, a conductive film of which a second conductive pattern is formed, (d) forming a contact hole, at a predetermined location, in both the conductive film and the insulation interlayer, so that the contact hole reaches the first conductive pattern, (e) forming the conductive layer at least in the contact hole, to make an electrical connection between the conductive film and the first conductive pattern, and (f) subsequent to the formation of the conductive film by step (e), selectively etching the conductive film and the conductive layer, to form said second conductive pattern. In an alternative embodiment, the second conductive pattern is obtained by selectively etching the conductive film prior to the formation of the contact hole, and the electrical connection is formed by selective CVD.

摘要翻译： 公开了一种通过接触通孔进行导体层之间的连接的方法，包括以下步骤：（a）在半导体衬底上形成第一导电图案，（b）形成绝缘夹层以使其覆盖第一导电图案，（c） 在绝缘中间层上形成导电膜，其中形成第二导电图案，（d）在预定位置在导电膜和绝缘中间层中形成接触孔，使得接触孔到达第一导电图案 导电图案，（e）至少在接触孔中形成导电层，以在导电膜和第一导电图案之间形成电连接，以及（f）在通过步骤（e）形成导电膜之后， 选择性地蚀刻导电膜和导电层，以形成所述第二导电图案。 在替代实施例中，通过在形成接触孔之前选择性地蚀刻导电膜而获得第二导电图案，并且通过选择性CVD形成电连接。

公开(公告)号：US4497108A

公开(公告)日：1985-02-05

申请号：US495483

申请日：1983-05-17

申请人： Kei Kurosawa

发明人： Kei Kurosawa

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76 ,  H01L21/76205 ,  H01L21/76224 ,  Y10S438/981

摘要： A method of manufacturing a semiconductor device wherein a thickness of an insulating film at a peripheral portion of an element formation region of a semiconductor substrate is increased. The feature of this method is that an antioxidant film is formed on the element formation region and subsequently said semiconductor substrate is exposed to an oxygen atmosphere, thereby locally oxidizing that portion of the film which surrounds said element formation region.

摘要翻译： 一种制造半导体器件的方法，其中在半导体衬底的元件形成区域的周边部分处的绝缘膜的厚度增加。 该方法的特征在于，在元件形成区域上形成抗氧化剂膜，随后将所述半导体衬底暴露于氧气氛，从而局部氧化围绕所述元件形成区域的膜的该部分。

公开(公告)号：US4472874A

公开(公告)日：1984-09-25

申请号：US384648

申请日：1982-06-03

申请人： Kei Kurosawa ,  Tadashi Shibata

发明人： Kei Kurosawa ,  Tadashi Shibata

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L21/263 ,  H01L21/225 ,  H01L7/54

CPC分类号： H01L29/0638 ,  H01L21/26513 ,  H01L21/76216

摘要： A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a predetermined semiconductor element region of a semiconductor substrate; (b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; (c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; (d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; (e) burying insulation material in the groove; and (f) forming a semiconductor element on the predetermined semiconductor element region.

摘要翻译： 一种用于制造集成电路器件的方法，其中半导体元件由绝缘材料隔离，包括以下步骤：（a）在半导体衬底的预定半导体元件区域上提供掩模图案; （b）使用掩模图案作为离子注入掩模，将与衬底相同导电类型的第一离子注入杂质引入衬底; （c）蚀刻基板并使用掩模图案形成凹槽，使得杂质的一部分至少保留在凹槽的侧壁中的掩模图案下方; （d）通过沟槽将与衬底相同的导电类型的第二离子注入杂质引入衬底; （e）将绝缘材料埋在槽中; 和（f）在预定的半导体元件区域上形成半导体元件。