公开(公告)号：US4270220A

公开(公告)日：1981-05-26

申请号：US70817

申请日：1979-08-29

申请人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

发明人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

IPC分类号： H03J5/02 ,  H04B1/26

CPC分类号： H03J5/0263

摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

摘要翻译： 一种在其调谐电路的本地振荡器中采用可变电容二极管的电子调谐型电视接收机，其包括分别存储表示与多个通道对应的调谐电压的多个数字数据的存储器，使得对应于 所选择的通道可以应用于调谐电路中的可变电容二极管，D / A转换器将对应于所选通道的数字数据转换为要提供给可变电容二极管的模拟电压，以及调谐电压控制电路，其功能 以预定速率顺序地修改从存储器读出的所选通道的数字数据，直到在调谐电路中达到调谐点，并且将该信号顺序地施加到D / A转换器，由此调谐电路 可以调谐到所选择的频道，而不管v的操作特性的长期和其他变化 可调电容二极管。

公开(公告)号：US5784637A

公开(公告)日：1998-07-21

申请号：US414157

申请日：1995-03-31

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

摘要翻译： 形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线 或输入/输出端口）和可变逻辑电路（或子处理器）。 可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。 可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。 存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

公开(公告)号：US5627989A

公开(公告)日：1997-05-06

申请号：US308548

申请日：1994-09-21

申请人： Hideo Nakamura ,  Terumi Sawase

发明人： Hideo Nakamura ,  Terumi Sawase

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/17 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7842 ,  G06F15/786

摘要： The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal; wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.

公开(公告)号：US5426744A

公开(公告)日：1995-06-20

申请号：US203761

申请日：1994-03-01

申请人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

发明人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

IPC分类号： G06F9/24 ,  G06F9/38 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

CPC分类号： G06F9/3879 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867 ,  G06F9/24 ,  G06F9/3897

摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

摘要翻译： 本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。 形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。 结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。 可以通过任意形成的逻辑功能来满足各种用户的需求规格。

公开(公告)号：US4920518A

公开(公告)日：1990-04-24

申请号：US329515

申请日：1989-03-28

申请人： Hideo Nakamura ,  Terumi Sawase

发明人： Hideo Nakamura ,  Terumi Sawase

IPC分类号： G11C7/24 ,  G11C16/22

CPC分类号： G11C16/22 ,  G11C7/24

摘要： A semiconductor integrated circuit with a non-volatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether operations such as programming (i.e., writing), erasing or reading with respect to the data memory elements will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element. In other words, data security in an arbitrary area of the matrix can be accomplished based on the content of the protecting data memory element.

公开(公告)号：US4744062A

公开(公告)日：1988-05-10

申请号：US854889

申请日：1986-04-23

申请人： Hideo Nakamura ,  Terumi Sawase

发明人： Hideo Nakamura ,  Terumi Sawase

IPC分类号： G11C7/24 ,  G11C16/22 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C16/22 ,  G11C7/24

摘要： A semiconductor integrated circuit with a nonvolatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether operations such as programming (i.e., writing), erasing or reading with respect to the data memory elements will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element. In other words, data security in an arbitrary area of the matrix can be accomplished based on the content of the protecting data memory element.

摘要翻译： 具有非易失性存储器的半导体集成电路具有以矩阵形式布置的多个非易失性数据存储器元件和用于根据指定矩阵中的位置的地址信号从存储器元件读取数据的装置。 用于存储至少一位保护数据的保护数据存储元件设置在矩阵中。 根据保护数据存储元件的内容确定是否允许或禁止关于数据存储器元件的编程（即写入），擦除或读取的操作。 换句话说，可以基于保护数据存储元件的内容来实现矩阵的任意区域中的数据安全性。

公开(公告)号：US5511211A

公开(公告)日：1996-04-23

申请号：US102156

申请日：1993-08-04

申请人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

发明人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F9/445 ,  G06F15/78 ,  G06F9/312 ,  G06F13/40 ,  G06F15/20

CPC分类号： G06F8/60 ,  G06F15/7814 ,  G06F9/24

摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

摘要翻译： 在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据 将系统的所需规格和功能写入逻辑功能块。 由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。 半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。

公开(公告)号：US5428808A

公开(公告)日：1995-06-27

申请号：US217826

申请日：1994-03-25

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

公开(公告)号：US5410718A

公开(公告)日：1995-04-25

申请号：US795985

申请日：1991-11-22

申请人： Shigeki Masumura ,  Tatsuya Aizawa ,  Kazuo Naito ,  Yoshiyuki Miwa ,  Hideo Nakamura ,  Terumi Sawase ,  Yasushi Akao

发明人： Shigeki Masumura ,  Tatsuya Aizawa ,  Kazuo Naito ,  Yoshiyuki Miwa ,  Hideo Nakamura ,  Terumi Sawase ,  Yasushi Akao

IPC分类号： G06F13/38 ,  G06F15/78 ,  G11C7/00 ,  G06F12/00

CPC分类号： G06F15/7867 ,  G06F15/7814

摘要： A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities.

摘要翻译： 单片微计算机包括微处理器，用于执行外围功能的子处理器，用于控制来自外部设备的输入/输出操作的外部端口和用于从内部输入多个数据的多功能逻辑存储器 至少一个微处理器，子处理器和外部端口，并且根据预定的优先级从多个数据中选择写入数据。

公开(公告)号：US4974208A

公开(公告)日：1990-11-27

申请号：US501542

申请日：1990-03-30

申请人： Hideo Nakamura ,  Terumi Sawase

发明人： Hideo Nakamura ,  Terumi Sawase

IPC分类号： G11C7/24 ,  G11C16/22

CPC分类号： G11C16/22 ,  G11C7/24

摘要： A microcomputer with a non-volatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether a programming (writing), erasing or reading operation with respect to the data memory elements is to be allowed or inhibited is determined in accordance with the contents of the protecting data memory element which are read out in response to the address signal.