公开(公告)号：US4270220A

公开(公告)日：1981-05-26

申请号：US70817

申请日：1979-08-29

申请人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

发明人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

IPC分类号： H03J5/02 ,  H04B1/26

CPC分类号： H03J5/0263

摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

摘要翻译： 一种在其调谐电路的本地振荡器中采用可变电容二极管的电子调谐型电视接收机，其包括分别存储表示与多个通道对应的调谐电压的多个数字数据的存储器，使得对应于 所选择的通道可以应用于调谐电路中的可变电容二极管，D / A转换器将对应于所选通道的数字数据转换为要提供给可变电容二极管的模拟电压，以及调谐电压控制电路，其功能 以预定速率顺序地修改从存储器读出的所选通道的数字数据，直到在调谐电路中达到调谐点，并且将该信号顺序地施加到D / A转换器，由此调谐电路 可以调谐到所选择的频道，而不管v的操作特性的长期和其他变化 可调电容二极管。

公开(公告)号：US4308596A

公开(公告)日：1981-12-29

申请号：US81890

申请日：1979-10-04

申请人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

发明人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C16/26 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10

摘要： In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

摘要翻译： 在每个具有至少栅极，衬底，源极和漏极的存储器单元的存储器阵列中，当衬底和源极和漏极处于相同的电位时，当存在电位差Vp时，进行写入操作 衬底和源极和漏极以及栅极处的电位。 当门和衬底之间存在电位差Vp时，存储的内容被擦除。 当存在基板和栅极之间的电位差Vp以及基板与源极和漏极之间存在电势差Vwd时，防止存储条件发生变化。 当这样的存储器阵列被部分地擦除时，通过在源极和漏极之间施加电压Vwd和电池的衬底之间施加电压V p来在单元的栅极和衬底之间施加电压V p来顺序地驱动不被擦除的单元， 对基板和电池栅极具有相同的电位。

公开(公告)号：US5784637A

公开(公告)日：1998-07-21

申请号：US414157

申请日：1995-03-31

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

摘要翻译： 形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线 或输入/输出端口）和可变逻辑电路（或子处理器）。 可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。 可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。 存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

公开(公告)号：US5426744A

公开(公告)日：1995-06-20

申请号：US203761

申请日：1994-03-01

申请人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

发明人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

IPC分类号： G06F9/24 ,  G06F9/38 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

CPC分类号： G06F9/3879 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867 ,  G06F9/24 ,  G06F9/3897

摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

摘要翻译： 本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。 形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。 结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。 可以通过任意形成的逻辑功能来满足各种用户的需求规格。

公开(公告)号：US5321845A

公开(公告)日：1994-06-14

申请号：US94920

申请日：1993-07-22

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

公开(公告)号：US5175840A

公开(公告)日：1992-12-29

申请号：US726113

申请日：1991-06-21

申请人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

发明人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

IPC分类号： G06F12/14

CPC分类号： G06F12/1433

摘要： Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate or body. The second inhibition means is coupled to the data bus and provides a second inhibiting operation to prevent access operations to the memory from outside the semiconductor body via the data bus and permanently disables the access operations to the memory irrespective of a releasing or termination of the first inhibiting operation after the second inhibiting operation has taken effect.

摘要翻译： 电可擦除可编程只读存储器（EEPROM）的易测试性和数据安全性可以通过设置焊盘和输入/输出（I / O）电路来实现，该电路提供半导体衬底上的EEPROM测试所需的地址，数据和控制信号， 通过在基板上布置由EEPROM器件组成的两级测试I / O截取电路，使得一旦完成测试，由于具有内置的数据安全功能，防止了对半导体衬底之外的非法存取。 具有这种能力的微型计算机设置有用于处理数据的中央处理单元（CPU），诸如EEPROM的存储器，其通过公共总线（其传送数据，地址和控制信号）与CPU进行内部通信，其他 比在测试模式期间以及提供安全性的第一和第二抑制电路。 第一禁止电路耦合到数据总线，并提供第一禁止操作以防止对存储器的访问操作。 第一抑制电路根据来自半导体衬底或主体外部的信号来释放第一禁止操作。 第二禁止装置耦合到数据总线，并且提供第二禁止操作，以防止经由数据总线从半导体主体外部对存储器的访问操作，并且永久地禁用对存储器的访问操作，而不管第一 第二禁止操作之后的禁止操作已经起作用。

公开(公告)号：US5511211A

公开(公告)日：1996-04-23

申请号：US102156

申请日：1993-08-04

申请人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

发明人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F9/445 ,  G06F15/78 ,  G06F9/312 ,  G06F13/40 ,  G06F15/20

CPC分类号： G06F8/60 ,  G06F15/7814 ,  G06F9/24

摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

摘要翻译： 在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据 将系统的所需规格和功能写入逻辑功能块。 由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。 半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。

公开(公告)号：US5428808A

公开(公告)日：1995-06-27

申请号：US217826

申请日：1994-03-25

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

公开(公告)号：US4620292A

公开(公告)日：1986-10-28

申请号：US700908

申请日：1985-02-12

申请人： Yoshimune Hagiwara ,  Shizuo Sugiyama ,  Narimichi Maeda ,  Osamu Yumoto ,  Takashi Akazawa ,  Masahito Kobayashi ,  Yasuhiro Kita ,  Yuzo Kita

发明人： Yoshimune Hagiwara ,  Shizuo Sugiyama ,  Narimichi Maeda ,  Osamu Yumoto ,  Takashi Akazawa ,  Masahito Kobayashi ,  Yasuhiro Kita ,  Yuzo Kita

IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/50 ,  G06F7/57 ,  G06F7/76 ,  G06F17/10 ,  H03M7/24

CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F2207/3856 ,  G06F7/49921

摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

公开(公告)号：US4577154A

公开(公告)日：1986-03-18

申请号：US517407

申请日：1983-07-26

申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

IPC分类号： G01R22/00 ,  G01R21/127 ,  G06G7/161 ,  G06G7/186 ,  H03K7/06 ,  H03K7/08 ,  H03M1/50 ,  H03M1/82 ,  H03K5/05

CPC分类号： H03M1/82 ,  H03K7/08

摘要： A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

摘要翻译： 一种脉冲宽度调制电路，通过将简单的电路加到现有的脉宽调制电路上，可以消除三角波信号的偏移电压和比较器的偏移电压相对于时间的脉冲宽度调制的平均误差。 本发明还涉及使用上述脉冲宽度调制电路的两个模拟信号的乘积的积分电路。 本发明的原理结合了用于消除三角波信号的偏移的电路，通过在每个预定周期内相对于三角波信号相对于输入信号或输入信号反转三角波信号， 电路，用于通过反相比较器的输出来消除比较器的偏移，并且如果输入信号不被反相则替换比较器的输入端，或者如果输入信号反相则连接比较器的输入端。