利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.036 秒)

    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip
    2.
    发明授权
    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip 失效
    集成在半导体芯片上的单片半导体集成电路器件和微计算机

    公开(公告)号：US5784637A

    公开(公告)日：1998-07-21

    申请号：US414157

    申请日：1995-03-31

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

    摘要翻译： 形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线 或输入/输出端口）和可变逻辑电路（或子处理器）。 可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。 可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。 存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

    Single-chip microcomputer
    3.
    发明授权
    Single-chip microcomputer 失效
    单片机

    公开(公告)号：US5428808A

    公开(公告)日：1995-06-27

    申请号：US217826

    申请日：1994-03-25

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

    摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

    Method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions
    4.
    发明授权
    Method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions 失效
    用于灵活地开发数据处理系统的方法，包括在功能检查之后重写非易失性存储器元件中的指令，指示所需功能的失败

    公开(公告)号：US5511211A

    公开(公告)日：1996-04-23

    申请号：US102156

    申请日：1993-08-04

    申请人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

    发明人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F9/445 ,  G06F15/78 ,  G06F9/312 ,  G06F13/40 ,  G06F15/20

    CPC分类号： G06F8/60 ,  G06F15/7814 ,  G06F9/24

    摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

    摘要翻译： 在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据 将系统的所需规格和功能写入逻辑功能块。 由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。 半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。

    Single chip microprocessor for satisfying requirement specification of users
    5.
    发明授权
    Single chip microprocessor for satisfying requirement specification of users 失效
    单芯片微处理器，用于满足用户的要求规格

    公开(公告)号：US5426744A

    公开(公告)日：1995-06-20

    申请号：US203761

    申请日：1994-03-01

    申请人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    发明人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    IPC分类号： G06F9/24 ,  G06F9/38 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

    CPC分类号： G06F9/3879 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867 ,  G06F9/24 ,  G06F9/3897

    摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

    摘要翻译： 本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。 形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。 结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。 可以通过任意形成的逻辑功能来满足各种用户的需求规格。

    Microprocessor and method for setting up its peripheral functions
    6.
    发明授权
    Microprocessor and method for setting up its peripheral functions 失效
    微处理器和设置其外设功能的方法

    公开(公告)号：US5307464A

    公开(公告)日：1994-04-26

    申请号：US621641

    申请日：1990-12-03

    申请人： Yasushi Akao ,  Shiro Baba ,  Yoshiyuki Miwa ,  Terumi Sawase ,  Yuji Sato ,  Shigeki Masumura

    发明人： Yasushi Akao ,  Shiro Baba ,  Yoshiyuki Miwa ,  Terumi Sawase ,  Yuji Sato ,  Shigeki Masumura

    IPC分类号： G06F13/12 ,  G06F15/78 ,  G06F13/00

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.

    摘要翻译： 单片微处理器1包括用于软件实现微处理器1的外围功能的CPU 2和子处理器5.子处理器5包括电可写内部存储设备微程序存储单元13和用于存储软件的顺控控制存储单元62 。 通过将软件写入存储器单元13和62来定义和/或修改外围功能。因此，定义和/或修改外围功能所花费的时间是编程存储器单元13和62所花费的时间。子 处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14.另外，微程序存储单元13向执行单元16提供微指令。顺序控制存储器 单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。 顺序控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11的选择顺序的信息。 每次读序列控制存储器单元62选择地址寄存器MAR0至MAR11中的一个。 存储在选择的地址寄存器中的微地址然后被提供给微程序存储单元13。