公开(公告)号：US20110228586A1

公开(公告)日：2011-09-22

申请号：US13044892

申请日：2011-03-10

申请人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US07341900B2

公开(公告)日：2008-03-11

申请号：US11186838

申请日：2005-07-22

申请人： Kazuya Nakayama ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa

发明人： Kazuya Nakayama ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa

IPC分类号： H01L21/338

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.

摘要翻译： 根据本发明的实施例的半导体器件具有通过栅极绝缘膜形成在半导体衬底上并具有狭缝部分的栅电极; 形成在栅电极的两个侧面和狭缝部的侧壁处的侧壁膜，并且填充狭缝部分的内部并在狭缝部分正下方覆盖栅极绝缘膜; 以及形成为覆盖栅电极和侧壁膜的层间绝缘膜。

公开(公告)号：US06958514B2

公开(公告)日：2005-10-25

申请号：US10405627

申请日：2003-04-03

申请人： Kazuya Nakayama ,  Bungo Tanaka ,  Nobuyuki Sato

发明人： Kazuya Nakayama ,  Bungo Tanaka ,  Nobuyuki Sato

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/4175 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying the gate wiring line, the impurity diffusion layer being for permitting extension of the remaining one of the source and drain layers of each unit cell up to the semiconductor substrate, and a second main electrode as formed at a back surface of the semiconductor substrate.

公开(公告)号：US5668194A

公开(公告)日：1997-09-16

申请号：US572581

申请日：1995-12-14

申请人： Naotami Ando ,  Toshiyuki Masuda ,  Takanori Hatano ,  Kazuya Nakayama

发明人： Naotami Ando ,  Toshiyuki Masuda ,  Takanori Hatano ,  Kazuya Nakayama

IPC分类号： C08F265/04 ,  C08F265/00 ,  C08F265/06 ,  C08F285/00 ,  C09D151/00 ,  H05K3/28 ,  C08L43/04

CPC分类号： C09D151/003 ,  C08F265/06 ,  C08F285/00 ,  H05K3/285 ,  Y10S525/902

摘要： This invention relates to a room temperature curing composition for use in various coatings for interior and exterior sidings, automotive bodies, household electrical appliances and plastic substrates and particularly for coatings required to have weather resistance and durability. The room temperature curing composition of this invention comprises an emulsion obtained by a multi-stage polymerization of monomers, said emulsion comprising emulsion particles, the core of which is formed by polymerization of (A) a silyl group-containing vinyl monomer, (B) an alkyl or cycloalkyl methacrylate whose alkyl moiety contains not less than 4 carbon atoms, and (C) a non-hydrophilic vinyl monomer other than (B) and the outer shell of which is formed by polymerization of (A), (B), (C) and (D) a hydrophilic vinyl monomer. The room temperature curing composition of this invention features a high stability of silyl groups it contains and a remarkably improved film-forming property even after prolonged storage. Moreover, it is very satisfactory in mechanical stability, water resistance, durability and white enamel gloss.

摘要翻译： 本发明涉及室温固化组合物，其用于室内和外侧各种涂料，汽车车身，家用电器和塑料基材，特别是用于具有耐候性和耐久性的涂层。 本发明的室温固化组合物包含通过单体多阶段聚合获得的乳液，所述乳液包含乳液颗粒，其核心通过（A）含甲硅烷基的乙烯基单体的聚合形成，（B） 烷基部分含有不少于4个碳原子的烷基或环烷基甲基丙烯酸酯，（C）除（B）以外的非亲水性乙烯基单体，其外壳由（A），（B）， （C）和（D）亲水性乙烯基单体。 本发明的室温固化组合物特征在于其含有的甲硅烷基的稳定性高，即使在长时间储存​​后也具有显着改善的成膜性能。 此外，机械稳定性，耐水性，耐久性和白色搪瓷光泽度非常令人满意。

公开(公告)号：US5554862A

公开(公告)日：1996-09-10

申请号：US183364

申请日：1994-01-19

申请人： Ichiro Omura ,  Mitsuhiko Kitagawa ,  Kazuya Nakayama ,  Masakazu Yamaguchi

发明人： Ichiro Omura ,  Mitsuhiko Kitagawa ,  Kazuya Nakayama ,  Masakazu Yamaguchi

IPC分类号： H01L29/745 ,  H01L29/749 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/749

摘要： In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.

摘要翻译： 在功率半导体器件中，在p发射极层上形成n基极。 在n基层上，横向形成p基层，n发射极层和高浓度p层。 在p基层中，n型源层与n型发射极层隔开规定的距离。 在n-发射极层中，与高浓度p层隔开规定的距离形成p源层。 在由n源层和n发射极层夹在的区域上经由第一栅极绝缘膜形成第一栅电极。 在由高浓度p层和p源层夹着的区域上经由第二栅极绝缘膜形成第二栅电极。 在p发射极层上形成第一主电极。 第二主电极形成为与p基层，n源层和p源层接触。

公开(公告)号：US08422270B2

公开(公告)日：2013-04-16

申请号：US13044892

申请日：2011-03-10

申请人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US08008715B2

公开(公告)日：2011-08-30

申请号：US12185630

申请日：2008-08-04

申请人： Yusuke Kawaguchi ,  Kazuya Nakayama ,  Tsuyoshi Ohta ,  Takeshi Uchihara ,  Takahiro Kawano ,  Yuji Kato

发明人： Yusuke Kawaguchi ,  Kazuya Nakayama ,  Tsuyoshi Ohta ,  Takeshi Uchihara ,  Takahiro Kawano ,  Yuji Kato

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7811

摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.

摘要翻译： 提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

公开(公告)号：USRE40705E1

公开(公告)日：2009-05-05

申请号：US10101778

申请日：2002-03-21

申请人： Kazuya Nakayama ,  Koichi Sugiyama

发明人： Kazuya Nakayama ,  Koichi Sugiyama

IPC分类号： H01L29/76

CPC分类号： H01L29/0834 ,  H01L29/32 ,  H01L29/7395

摘要： A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg [F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [Ω], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vt−Voff|≧0.5·Cg·Rg·(dV/dt).

摘要翻译： 提供一种高击穿电压半导体装置，其中，当栅极电极的形成沟道的部分的栅极电容为Cg [F]时，栅极部分的沟道长度方向的电阻 形成通道的电极为RgΩ，要施加到栅电极的阈值电压，其施加允许漏极电流的流动为Vth [V]，要施加的电压 到栅电极切断漏极电流为Voff [V]，并且在切断漏极电流时每单位时间的漏极电压的增加比为dV / dt [V / s]，以下条件 满足：<？in-line-formula description =“In-line formula”end =“lead”？> | Vt-Voff |> = 0.5.Cg.Rg。（dV / dt） 公式描述=“内联公式”end =“tail”？>

公开(公告)号：US20050121718A1

公开(公告)日：2005-06-09

申请号：US11037158

申请日：2005-01-19

申请人： Kazuya Nakayama ,  Bungo Tanaka ,  Nobuyuki Sato

发明人： Kazuya Nakayama ,  Bungo Tanaka ,  Nobuyuki Sato

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/4175 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying the gate wiring line, the impurity diffusion layer being for permitting extension of the remaining one of the source and drain layers of each unit cell up to the semiconductor substrate, and a second main electrode as formed at a back surface of the semiconductor substrate.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的半导体层，多个单元电池，每个单元电池具有设置并形成在半导体层上方的具有栅极电极的结构以具有条状形状并具有源极层和 形成在所述半导体层中的具有条状形状的漏极层，用于将所述单元电池的各个栅电极相互连接在一起的栅极布线;形成在覆盖所述栅电极的电介质膜上的第一主电极和所述栅极布线 并与每个单元电池的源极层和漏极层中的任何一个接触;在半导体层中仅形成在栅极布线的正下方的部分的深度到达半导体基板的深度的杂质扩散层，该部分是 从每个单位单元和部分的源层和漏层中的剩余部分的下方的部分中选择 在栅极布线的下方，杂质扩散层用于允许每个单元电池的剩余的一个源极和漏极层延伸到半导体衬底;以及第二主电极，形成在半导体衬底的背面 。

公开(公告)号：US06323831B1

公开(公告)日：2001-11-27

申请号：US09153086

申请日：1998-09-15

申请人： Tomio Ono ,  Tadashi Sakai ,  Naoshi Sakuma ,  Kazuya Nakayama

发明人： Tomio Ono ,  Tadashi Sakai ,  Naoshi Sakuma ,  Kazuya Nakayama

IPC分类号： G09G322

CPC分类号： H01J3/022 ,  H01J7/44 ,  H01J19/78

摘要： An electron emitting comprising an emitter electrode for emitting electrons when applied with an electric field, a gate electrode for extracting the electrons emitted from the emitter electrode, when applied with a voltage from a signal source, the voltage being positive with respect to the emitter electrode, an anode electrode connected to a load, for collecting the electrons extracted by the gate electrode, and for passing an anode current, and a gate resistor connected between the signal source and the gate electrode, for reducing a gate current flowing in the gate electrode, without changing an anode current flowing in the anode, and for lowering a gate voltage by utilizing a voltage drop cause by the gate current.

摘要翻译： 一种电子发射器，包括用于在施加电场时发射电子的发射极电极，用于从发射极发射的电子提取的栅电极，当施加来自信号源的电压时，该电压相对于发射电极为正 连接到负载的阳极，用于收集由栅电极提取的电子和用于通过阳极电流，以及连接在信号源和栅电极之间的栅极电阻，用于减少在栅电极中流动的栅极电流 ，而不改变在阳极中流动的阳极电流，并且通过利用由栅极电流引起的电压降降低栅极电压。