公开(公告)号：US5804479A

公开(公告)日：1998-09-08

申请号：US694665

申请日：1996-08-09

申请人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

发明人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  H01L27/105

摘要： The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

摘要翻译： 当通过在覆盖信息处理的上电极的BPSG膜上布置第一层布线来蚀刻和平坦化氧化硅膜时，提高作为较高海拔部分的存储器阵列的氧化硅膜的回蚀量。 仅在外围电路中存储电容元件，但不将其布置在存储器阵列中。 因此，获得具有堆叠电容器结构的DRAM，使得存储器阵列和外围电路之间的电平差减小，并且布线和连接孔的形成容易。

公开(公告)号：US5578849A

公开(公告)日：1996-11-26

申请号：US341966

申请日：1994-11-16

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

摘要翻译： 存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个存储单元具有开关晶体管和信息存储电容器。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。

公开(公告)号：US06649956B2

公开(公告)日：2003-11-18

申请号：US10227799

申请日：2002-08-27

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

公开(公告)号：US06483136B1

公开(公告)日：2002-11-19

申请号：US09446302

申请日：2000-04-14

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

公开(公告)号：US07042038B2

公开(公告)日：2006-05-09

申请号：US10653889

申请日：2003-09-04

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

公开(公告)号：US5933724A

公开(公告)日：1999-08-03

申请号：US703067

申请日：1996-08-26

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： G03F1/28 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

摘要翻译： 使用相移掩模来制造包括导体图案的半导体集成电路器件，其中图案化导体条的线宽或图案化导体条之间的空间不是恒定的。 对于对应于导体图案的掩模中的主要透明区域，提供辅助图案段以补偿由线宽或空间的变化引起的透射光的相位分布的变化。 或者，调节导体条之间的空间以抑制透射光的相分布的变化。 辅助图案片段是否应该具有相移功能是根据主透明区域的配置来确定的。

公开(公告)号：US6077735A

公开(公告)日：2000-06-20

申请号：US708104

申请日：1996-08-28

申请人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

发明人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L21/76218 ,  H01L21/823493 ,  H01L21/823878

摘要： A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

摘要翻译： 制造半导体器件的方法，其能够通过去除与深孔形成相关的LOCOS氧化的残留应力来控制杂质浓度和精细图案化。 形成用于分离半导体衬底的主平面上的元件区域的选择性氧化物层，例如p型硅衬底1.在包括选择性氧化物层的表面上形成掩模（例如光致抗蚀剂47） 通过掩模中的开口引入与半导体衬底的导电类型相反的导电类型的杂质（例如磷）。 然后，通过引入杂质形成深阱（例如n型深阱50），通过高温处理退火选择性氧化物膜。

公开(公告)号：US5937290A

公开(公告)日：1999-08-10

申请号：US862992

申请日：1997-05-27

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  Y10S438/942

摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

摘要翻译： 在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成 半导体衬底上的氧化膜，位线具有直段和突出段。 每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。 直线段和突出段通过两个单独的曝光步骤分别形成。

公开(公告)号：US06281071B1

公开(公告)日：2001-08-28

申请号：US09317999

申请日：1999-05-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。

公开(公告)号：US5753550A

公开(公告)日：1998-05-19

申请号：US620867

申请日：1996-03-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 在第一方面中，电容器元件所连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成 在高压下 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。