公开(公告)号：US5578849A

公开(公告)日：1996-11-26

申请号：US341966

申请日：1994-11-16

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

摘要翻译： 存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个存储单元具有开关晶体管和信息存储电容器。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。

公开(公告)号：US6023084A

公开(公告)日：2000-02-08

申请号：US174332

申请日：1998-10-19

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

摘要翻译： 半导体存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，并且相邻两个存储单元的晶体管的第二半导体区域连接到 各信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构相对于分别在一个位线导体的相对侧上相邻的相邻第一和第二位线导体下形成的一系列存储单元对单元结构位置移位，使得 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于邻近位线连接导体 形成在一个位线导体下的存储单元对单元结构。

公开(公告)号：US5831300A

公开(公告)日：1998-11-03

申请号：US731489

申请日：1996-10-16

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to the series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

摘要翻译： 半导体存储器件具有半导体衬底，字线导体和位线导体以及设置在字线导体和位线导体之间的交叉点处的存储单元。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构相对于分别形成在一个位线导体的相对侧上相邻的第一和第二位线导体之下的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。

公开(公告)号：US5933726A

公开(公告)日：1999-08-03

申请号：US709203

申请日：1996-08-27

申请人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

发明人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

摘要翻译： 诸如动​​态RAM的半导体器件及其制造方法。 在p型硅衬底（1）的顶部上沿着取向方向以规定的间隔放置多个堆叠的电池电容器。 每个电容器具有几乎垂直的圆柱形下电极（圆柱形多晶硅层（96）），电介质膜（氮化硅膜（77））和上电极（由多晶硅制成的板电极（78））。 排列方向上的间隔小于下电极的内径。

公开(公告)号：US5804479A

公开(公告)日：1998-09-08

申请号：US694665

申请日：1996-08-09

申请人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

发明人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  H01L27/105

摘要： The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

摘要翻译： 当通过在覆盖信息处理的上电极的BPSG膜上布置第一层布线来蚀刻和平坦化氧化硅膜时，提高作为较高海拔部分的存储器阵列的氧化硅膜的回蚀量。 仅在外围电路中存储电容元件，但不将其布置在存储器阵列中。 因此，获得具有堆叠电容器结构的DRAM，使得存储器阵列和外围电路之间的电平差减小，并且布线和连接孔的形成容易。

公开(公告)号：US5933724A

公开(公告)日：1999-08-03

申请号：US703067

申请日：1996-08-26

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： G03F1/28 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

摘要翻译： 使用相移掩模来制造包括导体图案的半导体集成电路器件，其中图案化导体条的线宽或图案化导体条之间的空间不是恒定的。 对于对应于导体图案的掩模中的主要透明区域，提供辅助图案段以补偿由线宽或空间的变化引起的透射光的相位分布的变化。 或者，调节导体条之间的空间以抑制透射光的相分布的变化。 辅助图案片段是否应该具有相移功能是根据主透明区域的配置来确定的。

公开(公告)号：US6060352A

公开(公告)日：2000-05-09

申请号：US15073

申请日：1998-01-28

申请人： Toshihiro Sekiguchi ,  Hideo Aoki ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Minoru Ohtsuka ,  Masayuki Yasuda ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Hideo Aoki ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Minoru Ohtsuka ,  Masayuki Yasuda ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.

摘要翻译： 提供了一种用于制造各自具有COB结构的DRAM的方法，以及通过该方法形成的半导体器件。 在一个实施例中，字线和/或位线被具有相对较小蚀刻速率的绝缘膜覆盖。 在由这些绝缘膜以自对准的方式限定的同时形成接触孔。

公开(公告)号：US06969649B2

公开(公告)日：2005-11-29

申请号：US10810884

申请日：2004-03-29

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L21/60 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。

公开(公告)号：US06753219B2

公开(公告)日：2004-06-22

申请号：US10226290

申请日：2002-08-23

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。

公开(公告)号：US5937290A

公开(公告)日：1999-08-10

申请号：US862992

申请日：1997-05-27

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  Y10S438/942

摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

摘要翻译： 在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成 半导体衬底上的氧化膜，位线具有直段和突出段。 每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。 直线段和突出段通过两个单独的曝光步骤分别形成。