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    Trilayer resist scheme for gate etching applications
    12.
    发明申请
    Trilayer resist scheme for gate etching applications 失效

    公开(公告)号：US20080045011A1

    公开(公告)日：2008-02-21

    申请号：US11506227

    申请日：2006-08-18

    申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

    摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

    Self-aligned borderless contacts for high density electronic and memory device integration
    13.
    发明授权
    Self-aligned borderless contacts for high density electronic and memory device integration 有权
    用于高密度电子和存储器件集成的自对准无边界触点

    公开(公告)号：US08754530B2

    公开(公告)日：2014-06-17

    申请号：US12193339

    申请日：2008-08-18

    申请人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    发明人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    Trilayer resist scheme for gate etching applications
    14.
    发明授权
    Trilayer resist scheme for gate etching applications 有权
    栅极蚀刻应用的三层抗蚀剂方案

    公开(公告)号：US08084825B2

    公开(公告)日：2011-12-27

    申请号：US12245946

    申请日：2008-10-06

    申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L20/10

    CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

    摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

    摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION
    17.
    发明申请
    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权
    用于高密度电子和存储器件集成的自对准无边界联系

    公开(公告)号：US20100038723A1

    公开(公告)日：2010-02-18

    申请号：US12193339

    申请日：2008-08-18

    申请人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    发明人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
    18.
    发明申请
    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS 有权
    制造CMOS晶体管等离子体源和漏区的方法

    公开(公告)号：US20130012026A1

    公开(公告)日：2013-01-10

    申请号：US13611678

    申请日：2012-09-12

    申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    IPC分类号： H01L21/311

    CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

    摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

    摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

    Mixed lithography with dual resist and a single pattern transfer
    19.
    发明授权
    Mixed lithography with dual resist and a single pattern transfer 有权
    具有双光栅和单一图案转印的混合光刻

    公开(公告)号：US08334090B2

    公开(公告)日：2012-12-18

    申请号：US13015668

    申请日：2011-01-28

    申请人： Nicholas C. Fuller ,  Michael A. Guillorn ,  Balasubramanian S. Pranatharthi Haran ,  Jyotica V. Patel

    发明人： Nicholas C. Fuller ,  Michael A. Guillorn ,  Balasubramanian S. Pranatharthi Haran ,  Jyotica V. Patel

    IPC分类号： G03C5/00

    CPC分类号： G03F7/0035 ,  Y10S430/143 ,  Y10T428/24612 ,  Y10T428/24802

    摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译： 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。

    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS
    20.
    发明申请
    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS 失效
    制造CMOS晶体管等离子体侵入区的方法

    公开(公告)号：US20110278672A1

    公开(公告)日：2011-11-17

    申请号：US12779087

    申请日：2010-05-13

    申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L21/302

    CPC分类号： H01L27/092 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66757

    摘要： A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

    摘要翻译： 一种用于制造积极缩放的CMOS器件的凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控地形成薄体的沟道中的漏极的凹陷区域，远小于40nm的器件，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向异性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。