MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
    1.
    发明申请
    MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER 有权
    具有双重电阻和单模式传输的混合光刻

    公开(公告)号:US20090092799A1

    公开(公告)日:2009-04-09

    申请号:US11867428

    申请日:2007-10-04

    IPC分类号: G03C5/00 G03G7/00

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    Mixed lithography with dual resist and a single pattern transfer
    2.
    发明授权
    Mixed lithography with dual resist and a single pattern transfer 有权
    具有双光栅和单一图案转印的混合光刻

    公开(公告)号:US08334090B2

    公开(公告)日:2012-12-18

    申请号:US13015668

    申请日:2011-01-28

    IPC分类号: G03C5/00

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
    3.
    发明申请
    MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER 有权
    具有双重电阻和单模式传输的混合光刻

    公开(公告)号:US20110123779A1

    公开(公告)日:2011-05-26

    申请号:US13015668

    申请日:2011-01-28

    IPC分类号: B32B3/10

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    Mixed lithography with dual resist and a single pattern transfer
    4.
    发明授权
    Mixed lithography with dual resist and a single pattern transfer 有权
    具有双光栅和单一图案转印的混合光刻

    公开(公告)号:US07914970B2

    公开(公告)日:2011-03-29

    申请号:US11867428

    申请日:2007-10-04

    IPC分类号: G03C5/00

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES
    5.
    发明申请
    PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
    等离子体固化材料的等离子体刻蚀特性

    公开(公告)号:US20090174036A1

    公开(公告)日:2009-07-09

    申请号:US11969525

    申请日:2008-01-04

    IPC分类号: H01L29/30 G03F7/26

    CPC分类号: G03F7/40

    摘要: A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.

    摘要翻译: 公开了一种能够在光刻图案化之后显着降低线边缘粗糙度(LER)和线宽粗糙度(LEW)来制造半导体器件(即STI结构,栅极和互连)的方法。 本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外(VUV)发射和/或给定特征(在相同的蚀刻平台上)的一个蚀刻工艺,以引发增加的交联 的一个或多个图案形成材料,因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

    Self-aligned borderless contacts for high density electronic and memory device integration
    6.
    发明授权
    Self-aligned borderless contacts for high density electronic and memory device integration 有权
    用于高密度电子和存储器件集成的自对准无边界触点

    公开(公告)号:US08754530B2

    公开(公告)日:2014-06-17

    申请号:US12193339

    申请日:2008-08-18

    IPC分类号: H01L23/48

    摘要: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译: 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域,栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION
    7.
    发明申请
    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权
    用于高密度电子和存储器件集成的自对准无边界联系

    公开(公告)号:US20100038723A1

    公开(公告)日:2010-02-18

    申请号:US12193339

    申请日:2008-08-18

    IPC分类号: H01L29/00 H01L21/20

    摘要: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译: 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域,栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    Fin Fet device with independent control gate
    9.
    发明授权
    Fin Fet device with independent control gate 有权
    Fin Fet设备具有独立的控制门

    公开(公告)号:US09214529B2

    公开(公告)日:2015-12-15

    申请号:US13047132

    申请日:2011-03-14

    摘要: A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.

    摘要翻译: 一种具有独立控制栅极的FinFET器件,包括:绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管,所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极,其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域,所述控制栅极包括:氮化硅薄层; 和多个间隔件。