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    Programmable lookup table with dual input and output terminals in shift register mode
    12.
    发明授权
    Programmable lookup table with dual input and output terminals in shift register mode 有权
    可编程查找表，带有移位寄存器模式的双输入和输出端子

    公开(公告)号：US07215138B1

    公开(公告)日：2007-05-08

    申请号：US11152590

    申请日：2005-06-14

    申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

    发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1736 ,  H03K19/17728 ,  H03K19/1776

    摘要： A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N−1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N−2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

    摘要翻译： 用于集成电路（IC）的可编程查找表可选地在编程为用作移位寄存器逻辑时提供两个输入信号和两个输出信号到可编程IC的互连结构。 根据一个实施例，集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT），其中N是整数。 LUT可以被配置为用作具有输入信号移位和耦合到互连结构的一个输出信号的（2 **（N-1））位移位寄存器，或者作为二（2 **（N- 2）） - 具有耦合到互连结构的输入信号中的两个移位和两个输出信号的位移位寄存器。 在一些实施例中，移位寄存器的每个位包括LUT的两个存储单元，用作主锁存器的第一存储器单元和用作从锁存器的第二存储器单元。

    Integrated circuit having a programmable input structure with bounce capability
    13.
    发明授权
    Integrated circuit having a programmable input structure with bounce capability 有权
    具有可跳变能力的可编程输入结构的集成电路

    公开(公告)号：US07202698B1

    公开(公告)日：2007-04-10

    申请号：US11152358

    申请日：2005-06-14

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： A programmable input structure for a logic block provides the capability of “bouncing” a logic block input signal back to the interconnect structure of the integrated circuit, and/or to other input terminals of the logic block, without disabling other functions in the logic block. A programmable input multiplexer circuit selects one of the available signals from the interconnect structure, and passes the selected interconnect signal to a logic block. The signal can be disabled within the logic block by programming a bounce multiplexer circuit to select a static value (e.g., power high or ground) instead of the selected interconnect signal. Therefore, the selected signal is safely provided to the interconnect structure and/or another input multiplexer circuit, in addition to the logic block input terminal.

    摘要翻译： 用于逻辑块的可编程输入结构提供了将逻辑块输入信号“反弹”回集成电路的互连结构和/或逻辑块的其他输入端的能力，而不会使逻辑块中的其他功能不被禁止 。 可编程输入多路复用器电路从互连结构中选择一个可用信号，并将选定的互连信号传递给逻辑块。 可以通过编程反弹多路复用器电路来选择静态值（例如，功率高或接地）而不是所选择的互连信号，可以在逻辑块内禁止该信号。 因此，除了逻辑块输入端之外，所选择的信号被安全地提供给互连结构和/或另一个输入多路复用器电路。

    Integrated circuit having a programmable input structure with optional fanout capability
    14.
    发明授权
    Integrated circuit having a programmable input structure with optional fanout capability 有权
    集成电路具有可选的扇出功能的可编程输入结构

    公开(公告)号：US07196543B1

    公开(公告)日：2007-03-27

    申请号：US11151819

    申请日：2005-06-14

    申请人： Steven P. Young ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Trevor J. Bauer

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable input structure for a programmable logic circuit provides the capability of “fanning out” a selected signal to two or more input terminals of the programmable logic circuit, thereby increasing the routability of the logic block input signals. A logic block for an integrated circuit includes a programmable logic circuit and input multiplexers programmably selecting an input signal to provide to the programmable logic circuit. Also included in the integrated circuit are fan multiplexers that do not drive the programmable logic circuit directly. Instead, the fan multiplexers drive two or more of the input multiplexers that can, optionally, drive other input multiplexers in the same logic block, providing additional selection options among potential input signals. In some embodiments, the fan multiplexers are driven by global and/or regional clock signals. Thus, existing clock distribution structures can be used to provide high fanout input signals to the programmable logic circuit.

    摘要翻译： 用于可编程逻辑电路的可编程输入结构提供了将选定信号“扇出”到可编程逻辑电路的两个或多个输入端的能力，从而增加逻辑块输入信号的可路由性。 集成电路的逻辑块包括可编程逻辑电路和可编程选择输入信号以提供给可编程逻辑电路的输入多路复用器。 集成电路中还包括不直接驱动可编程逻辑电路的风扇多路复用器。 相反，风扇多路复用器驱动两个或更多个输入多路复用器，其可以可选地驱动相同逻辑块中的其他输入多路复用器，在电位输入信号之间提供附加的选择选项。 在一些实施例中，风扇多路复用器由全局和/或区域时钟信号驱动。 因此，现有的时钟分配结构可用于向可编程逻辑电路提供高扇出输入信号。

    Windowing circuit for aligning data and clock signals
    15.
    发明授权
    Windowing circuit for aligning data and clock signals 有权
    用于对准数据和时钟信号的窗口电路

    公开(公告)号：US06864715B1

    公开(公告)日：2005-03-08

    申请号：US10377461

    申请日：2003-02-27

    申请人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    发明人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    IPC分类号： G06F1/025 ,  H03K5/135 ,  H03K19/177 ,  H04L7/00 ,  G06F7/38 ,  H03D3/24 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G06F1/025 ,  H03K5/135 ,  H03K19/1774 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0041

    摘要： Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

    摘要翻译： 描述了用于对准数据和时钟信号的电路和方法。 根据一些实施例的电路将输入数据分成三个不同定时的数据信号：早期信号，中间信号和后期信号。 三个数据信号的定时可以相对于时钟信号共同移动。 此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。 三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。 可以监视早期和晚期信号以识别时钟和数据信号的相对时序的变化。 一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

    Large crossbar switch implemented in FPGA
    16.
    发明授权
    Large crossbar switch implemented in FPGA 有权
    在FPGA中实现大型交叉开关

    公开(公告)号：US06759869B1

    公开(公告)日：2004-07-06

    申请号：US10164508

    申请日：2002-06-05

    申请人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

    发明人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

    IPC分类号： H03K19177

    CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H04Q3/0004 ,  H04Q3/521 ,  H04Q2213/13076

    摘要： A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

    摘要翻译： 描述了使用FPGA实现交叉开关的方法。 不是使用通过通用FPGA路由资源路由的信号来控制交叉开关的连接，而是输入信号只带有交叉开关数据，连接由FPGA配置数据控制。 交叉开关分两部分实现：基本和恒定路由的模板，通过一维的交换机阵列传送输入信号，并在另一维度上输出阵列的信号，以及由连接表或算法控制的连接部分，以产生 部分重新配置比特流，其确定哪个输入信号要连接到哪个输出信号。

    Interconnect structure for a programmable logic device
    17.
    发明授权
    Interconnect structure for a programmable logic device 有权

    公开(公告)号：US06448808B2

    公开(公告)日：2002-09-10

    申请号：US09929977

    申请日：2001-08-15

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    IPC分类号： H01L2500

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17796

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

    FPGA interconnect structure with high-speed high fanout capability
    19.
    发明授权
    FPGA interconnect structure with high-speed high fanout capability 失效
    FPGA互连结构具有高速高扇出功能

    公开(公告)号：US5907248A

    公开(公告)日：1999-05-25

    申请号：US20369

    申请日：1998-02-09

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177 ,  H03K7/38

    CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away. According to a second aspect of the invention, high fanout signals can be distributed to any tile in the array. A signal on a horizontal long line traverses a row of tiles, in which it makes contact with the logic block in each tile through hex lines and single-length lines. The horizontal single-length lines connected to some horizontal hex lines can programmably drive vertical long lines. Using these programmable connections, the signal on the horizontal long line bus is transferred to the vertical long lines. From the vertical long lines, a high-fanout signal is delivered to an array of tiles.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径 和瓷砖有一段距离。 可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。 在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片之外，然后继续并连接到瓦片六瓦片。 在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。 根据本发明的第二方面，高扇出信号可以分布到阵列中的任何瓦片。 水平长线上的信号穿过一排瓦片，通过十六进制线和单条线与其接触每个瓦片中的逻辑块。 连接到一些水平六边形线的水平单线可以编程地驱动垂直的长线。 使用这些可编程连接，水平长线总线上的信号传输到垂直长线。 从垂直长线，高扇出信号被传送到一组瓦片。