公开(公告)号：US20160127164A1

公开(公告)日：2016-05-05

申请号：US14923428

申请日：2015-10-26

Applicant: MEDIATEK INC.

Inventor： Khurram Muhammad ,  Chih-Ming Hung

IPC: H04L27/26 ,  H04B1/04

CPC classification number: H04L27/2623 ,  H03F3/24 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/0491 ,  H04L27/365

Abstract: A transmitter circuit includes a frequency generation circuit configured to generate a local oscillator signal and a digital modulator configured to: receive data to be transmitted; quadrature modulate the received data to at least a first, Q, modulated value and a second, I, modulated value; examine the quadrature modulated data to determine if the first, Q, modulated value exceeds a limit, and in response thereto selectively modify the quadrature modulated values to a first modified, Q′, modulated value and a second modified, I′, modulated value thereby bringing only a value of the first modified, Q′, modulated value to within the limit. A local oscillator phase is selected in order to map the first modified, Q′, modulated value and second modified, I′, modulated value to desired quadrature values. A digital power amplifier, DPA, coupled to the digital quadrature modulator, is configured to amplify the quadrature modified modulated data.

Abstract translation: 发射机电路包括：频率产生电路，被配置为产生本地振荡器信号;以及数字调制器，被配置为：接收待传输的数据; 将接收的数据正交调制为至少第一调制值和第二调制值; 检查正交调制数据以确定第一Q调制值是否超过限制，并且响应于此，将正交调制值有选择地将正交调制值修改为第一修改后的调制值，调制值和第二修正I'调制值 仅将第一个修改后的Q'调制值的值设置在限制内。 选择本地振荡器相位以便将第一修改的Q'调制值和第二修改的I'调制值映射到期望的正交值。 耦合到数字正交调制器的数字功率放大器DPA被配置为放大正交修改的调制数据。

公开(公告)号：US20160127160A1

公开(公告)日：2016-05-05

申请号：US14920887

申请日：2015-10-23

Applicant: MEDIATEK INC.

Inventor： Khurram Muhammad ,  Dennis Mahoney

IPC: H04L27/00

CPC classification number: H04L27/0014 ,  H03L7/1976 ,  H04L2027/0018 ,  H04L2027/0055 ,  H04L2027/0069

Abstract: A circuit includes a frequency generation circuit having a phase locked loop, PLL, arranged to generate a carrier frequency; and a controller operably coupled to the frequency generation circuit and arranged to determine a frequency location of one or more signals output by the frequency generation circuit and provide a control signal thereto to adjust the carrier frequency generated by the frequency generation circuit. The controller is arranged to: cooperate with the PLL to introduce a frequency offset in the generated carrier frequency in a first frequency direction; and introduce a compensating frequency offset in a baseband transmit signal in a second frequency direction opposite to the first frequency direction.

Abstract translation: 电路包括频率产生电路，其具有被配置为产生载波频率的锁相环PLL; 以及控制器，其可操作地耦合到所述频率发生电路，并且被布置为确定由所述频率发生电路输出的一个或多个信号的频率位置，并提供其控制信号以调整由所述频率产生电路产生的载波频率。 所述控制器被配置为：与所述PLL配合以在所述生成的载波频率中在第一频率方向上引入频率偏移; 并且在与第一频率方向相反的第二频率方向上的基带发送信号中引入补偿频率偏移。

公开(公告)号：US11002829B2

公开(公告)日：2021-05-11

申请号：US15486887

申请日：2017-04-13

Applicant: MediaTek Inc.

Inventor： Chih-Ming Hung ,  Khurram Muhammad

IPC: G01S7/02 ,  G01S13/34 ,  G01S7/35 ,  G01S13/58 ,  G01S13/931 ,  H04J13/00 ,  H04J13/10

Abstract: Methods and apparatuses pertaining to radar interference mitigation are described. A processor associated with an apparatus may generate a plurality of wave frames such that one or more aspects of the plurality of wave frames vary from one wave frame to another wave frame of the plurality of wave frames. Each of the plurality of wave frames may respectively include a plurality of chirps. A wireless transmitter associated with the apparatus may transmit the plurality of wave frames. A wireless receiver associated with the apparatus may receive one or more reflected waves comprising at least a portion of one or more of the wave frames reflected by an object. The processor may determine a distance between the object and the apparatus, a speed of the objet, or both, based on an analysis of the one or more reflected waves.

公开(公告)号：US09584146B2

公开(公告)日：2017-02-28

申请号：US14886545

申请日：2015-10-19

Applicant: MediaTek Inc.

Inventor： Frank Op 't Eynde ,  Nathan Egan ,  Khurram Muhammad ,  Tien-Yu Lo ,  Chi-Lun Lo ,  Michael A. Ashburn

IPC: H03M1/10 ,  H03M1/12 ,  H03M3/00

CPC classification number: H03M1/109 ,  H03M1/1038 ,  H03M1/12 ,  H03M3/50

Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

Abstract translation: 描述了用于测量和补偿模数转换器的直流传递特性的系统和方法。 包括Σ-Δ调制器的测试信号发生器可以向ADC提供校准信号。 来自ADC的输出可以用陷波滤波器滤波，以抑制由Σ-Δ调制器引入的离散频率的量化噪声。 所得到的滤波信号可以与输入的数字信号与测试信号发生器进行比较，以确定ADC的传输特性。

公开(公告)号：US20140348264A1

公开(公告)日：2014-11-27

申请号：US14281902

申请日：2014-05-20

Applicant: MEDIATEK INC.

Inventor： Wen-Chieh Wang ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  I-Wen Liu ,  Khurram Muhammad ,  Chih-Ming Hung

IPC: H04B1/04 ,  H04L25/08 ,  H04L25/02

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract translation: 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。