公开(公告)号：US09504092B2

公开(公告)日：2016-11-22

申请号：US14668891

申请日：2015-03-25

Applicant: MediaTek Inc.

Inventor： Hsien-Chyi Chiou ,  Shu-Ping Shiu ,  Hong-Kai Hsu ,  Yuan-Hung Chung ,  Wei Wang ,  Ren-yuh Liang

IPC: H04L5/00 ,  H04W88/06 ,  H04B1/403 ,  H04L5/14

CPC classification number: H04W88/06 ,  H04B1/406 ,  H04L5/1469 ,  H04M2250/02 ,  H04M2250/06

Abstract: A system for the coexistence between a plurality of wireless communication modules sharing a single antenna includes an antenna, first and second transceiving paths, and first and second wireless communications modules. The first wireless communications module is coupled to a first transceiving path and transmits or receives first wireless signals via the first transceiving path. The second wireless communications module is coupled to the second transceiving path and transmits and receives second wireless signals via the first and the second transceiving paths, wherein signal strengths of the second wireless signals passing through the second transceiving path are attenuated by a certain level, and the attenuated second wireless signals are added to the first wireless signals when passing through the first transceiving path, wherein one of the first and the second communications module is a LTE module and the other one is a WLAN module.

Abstract translation: 共享单个天线的多个无线通信模块之间共存的系统包括天线，第一和第二收发路径以及第一和第二无线通信模块。 第一无线通信模块耦合到第一收发路径，并经由第一收发路径发送或接收第一无线信号。 第二无线通信模块耦合到第二收发路径，并且经由第一和第二收发路径发送和接收第二无线信号，其中通过第二收发路径的第二无线信号的信号强度衰减一定水平，并且 当经过第一收发路径时，衰减的第二无线信号被添加到第一无线信号，其中第一和第二通信模块中的一个是LTE模块，另一个是WLAN模块。

公开(公告)号：US20160322957A1

公开(公告)日：2016-11-03

申请号：US14821885

申请日：2015-08-10

Applicant: MEDIATEK Inc.

Inventor： Yuan-Hung Chung ,  Ming-Yeh Hsu

IPC: H03H11/04

CPC classification number: H03H11/0461 ,  H03F3/45273 ,  H03F2200/91 ,  H03H11/0405 ,  H03H11/0416 ,  H03H11/0466 ,  H03H11/1213 ,  H03H2011/0411

Abstract: A frequency selective circuit includes a first transistor, an impedance element, a first capacitive element, a second capacitive element, a second capacitive and a second transistor. The first transistor includes a first terminal, a second terminal and a control terminal. The impedance element is coupled between the first terminal and the control terminal of the first transistor. The first capacitive element is coupled to the first terminal of the first transistor. The second capacitive element is coupled to the control terminal of the first transistor. The second transistor includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the control terminal of the first transistor.

Abstract translation: 频率选择电路包括第一晶体管，阻抗元件，第一电容元件，第二电容元件，第二电容和第二晶体管。 第一晶体管包括第一端子，第二端子和控制端子。 阻抗元件耦合在第一晶体管的第一端子和控制端子之间。 第一电容元件耦合到第一晶体管的第一端。 第二电容元件耦合到第一晶体管的控制端。 第二晶体管包括第一端子，第二端子和控制端子，其中第二晶体管的控制端子耦合到第一晶体管的控制端子。

公开(公告)号：US09337644B2

公开(公告)日：2016-05-10

申请号：US13662851

申请日：2012-10-29

Applicant: MediaTek Inc.

Inventor： Bo-Shih Huang ,  Tsung-Ming Chen ,  Yuan-Hung Chung

IPC: H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06 ,  H02H3/20 ,  H02H9/04

CPC classification number: H02H3/20 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合在焊盘和电源线之间的阻抗装置以及耦合在焊盘和接地线之间的夹紧单元。

公开(公告)号：US09331472B2

公开(公告)日：2016-05-03

申请号：US14591254

申请日：2015-01-07

Applicant: MediaTek Inc

Inventor： Bo-Shih Huang ,  Tsung-Ming Chen ,  Yuan-Hung Chung

IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC classification number: H02H3/20 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line, wherein no ESD current flows through the impedance device when an ESD event occurs at the pad.

Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合在焊盘和电源线之间的阻抗装置以及耦合在焊盘和接地线之间的夹紧单元，其中当在焊盘处发生ESD事件时，ESD电流不流过阻抗器件。

公开(公告)号：US09508786B2

公开(公告)日：2016-11-29

申请号：US14886221

申请日：2015-10-19

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US09503052B1

公开(公告)日：2016-11-22

申请号：US14821885

申请日：2015-08-10

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Ming-Yeh Hsu

IPC: H03K5/00 ,  H03H11/04

CPC classification number: H03H11/0461 ,  H03F3/45273 ,  H03F2200/91 ,  H03H11/0405 ,  H03H11/0416 ,  H03H11/0466 ,  H03H11/1213 ,  H03H2011/0411

Abstract: A frequency selective circuit includes a first transistor, an impedance element, a first capacitive element, a second capacitive element, a second capacitive and a second transistor. The first transistor includes a first terminal, a second terminal and a control terminal. The impedance element is coupled between the first terminal and the control terminal of the first transistor. The first capacitive element is coupled to the first terminal of the first transistor. The second capacitive element is coupled to the control terminal of the first transistor. The second transistor includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the control terminal of the first transistor.

Abstract translation: 频率选择电路包括第一晶体管，阻抗元件，第一电容元件，第二电容元件，第二电容和第二晶体管。 第一晶体管包括第一端子，第二端子和控制端子。 阻抗元件耦合在第一晶体管的第一端子和控制端子之间。 第一电容元件耦合到第一晶体管的第一端。 第二电容元件耦合到第一晶体管的控制端。 第二晶体管包括第一端子，第二端子和控制端子，其中第二晶体管的控制端子耦合到第一晶体管的控制端子。

公开(公告)号：US20160065182A1

公开(公告)日：2016-03-03

申请号：US14468345

申请日：2014-08-26

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Jiunn-Nan Hwang ,  Yipin Wu ,  Tsung-Ying Tsai ,  Chin-Wei Huang

IPC: H03K3/012 ,  H03K17/687

CPC classification number: H03K17/687 ,  H03H11/0422 ,  H03K17/164 ,  H03K19/00346

Abstract: A digital circuit comprises a plurality of functional circuits and a finite state machine. Each functional circuit comprises a digital macro, a resistance control device and at least one device with capacitance. The digital macro is coupled to a ground. The resistance control device is electrically connected between the digital macro and an always-on power mesh. The at least one device with capacitance is electrically connected between the resistance control device and the ground. The finite state machine is electrically connected to the resistance control device, and is configured to adjust the resistance of the resistance control device.

Abstract translation: 数字电路包括多个功能电路和有限状态机。 每个功能电路包括数字宏，电阻控制装置和至少一个具有电容的装置。 数字宏耦合到地面。 电阻控制装置电连接在数字宏和永久在线功率网之间。 具有电容的至少一个装置电连接在电阻控制装置和地之间。 有限状态机电连接到电阻控制装置，并且被配置为调整电阻控制装置的电阻。

公开(公告)号：US20160049462A1

公开(公告)日：2016-02-18

申请号：US14748161

申请日：2015-06-23

Applicant: Mediatek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Yuan-Hung Chung

IPC: H01L49/02

CPC classification number: H01L28/86 ,  H01L23/5223 ,  H01L28/60 ,  H01L28/88 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract translation: 本发明提供一种半导体电容器结构。 半导体电容器结构包括第一金属层，第二金属层和第一介电层。 第一金属层被布置为半导体电容器结构的第一电极的一部分，并且第一金属层包括第一部分和第二部分。 第一部分形成为具有第一图案，并且第二部分连接到第一部分。 第二金属层被布置为半导体电容器结构的第二电极的一部分，并且第一介电层形成在第一金属层和第二金属层之间。

公开(公告)号：US08929847B2

公开(公告)日：2015-01-06

申请号：US14258038

申请日：2014-04-22

Applicant: Mediatek Inc.

Inventor： Yuan-Hung Chung ,  Yi-Shing Shih

IPC: H04B1/10 ,  H04B1/12 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/45 ,  H03D7/14

CPC classification number: H04B1/12 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/45475 ,  H03F2200/294 ,  H04L25/0278

Abstract: A signal processing circuit with noise cancellation includes an impedance matching unit and a transconductance stage. The impedance matching unit is disposed at a first path, and arranged to provide input impedance matching, wherein the impedance matching unit is a passive element, and the first path is coupled between a signal input port and a signal output port. The transconductance stage is disposed at a second path, and arranged to guide circuit introduced noise to the signal output port for noise cancellation at the signal output port, wherein the second path is coupled between the signal input port and the signal output port.

Abstract translation: 具有噪声消除的信号处理电路包括阻抗匹配单元和跨导级。 阻抗匹配单元设置在第一路径处，并且被布置成提供输入阻抗匹配，其中阻抗匹配单元是无源元件，并且第一路径耦合在信号输入端口和信号输出端口之间。 跨导级设置在第二路径处，并且被布置成引导电路引入的噪声到信号输出端口用于信号输出端口处的噪声消除，其中第二路径耦合在信号输入端口和信号输出端口之间。