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28 条记录 (耗时 0.032 秒)

    Methods and apparatus for constant-weight encoding and decoding
    12.
    发明申请
    Methods and apparatus for constant-weight encoding and decoding 有权
    用于恒权重编码和解码的方法和装置

    公开(公告)号：US20050122823A1

    公开(公告)日：2005-06-09

    申请号：US11036146

    申请日：2005-01-14

    申请人： William Cornelius ,  William Athas

    发明人： William Cornelius ,  William Athas

    IPC分类号： G06F5/00 ,  H03M7/02 ,  H03M13/23 ,  H03M13/41 ,  G11C8/00

    CPC分类号： G06F13/4027 ,  H03M13/23 ,  H03M13/41

    摘要： Methods and apparatus for spreading and concentrating information are taught. The present invention relates to constant-weight encoding of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, of the present invention, data transfer rates previously obtained only with differential architecture are achieved by only a small increase in line count above single ended architecture. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

    摘要翻译： 教授了传播和集中信息的方法和设备。 本发明涉及在并行数据线总线上的数据字的恒权重编码，同时允许跨越子字路径的信息通信。 在本发明的一个实施例中，仅通过差分架构获得的数据传输速率仅通过单端架构以上的行计数增加而实现。 例如，18位数据字需要22个用于传输的编码数据线，其中先前需要16行和32行来传输具有单端和差分架构的未编码数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。

    Method and apparatus for changing the clock frequency of a memory system
    14.
    发明申请
    Method and apparatus for changing the clock frequency of a memory system 有权
    用于改变存储器系统的时钟频率的方法和装置

    公开(公告)号：US20070234100A1

    公开(公告)日：2007-10-04

    申请号：US11367813

    申请日：2006-03-03

    申请人： Paul Baker ,  William Athas

    发明人： Paul Baker ,  William Athas

    IPC分类号： G06F1/04

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

    摘要： One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the clock frequency to the new clock frequency. More specifically, the system starts an iteration by slewing the clock frequency toward the new clock frequency by an increment to reach an intermediate frequency without interfering with normal memory-system operation. Next, the system signals a memory controller to pause normal memory system operation by completing or cancelling all in-flight or outstanding memory system operations and not accepting additional memory operation requests. Upon receiving an acknowledgement from the memory controller that all in-flight or outstanding memory operations have completed or terminated, the system signals the memory controller to cause a delay-locked loop (DLL) inside the memory system to relock to the intermediate frequency. When the DLL relocks to the intermediate frequency, the system completes the iteration by resuming normal memory system operation.

    摘要翻译： 本发明的一个实施例提供一种便于改变存储器系统中的时钟频率的系统。 在运行期间，系统接收到将时钟频率更改为新时钟频率的命令。 然后系统将时钟频率迭代地更改为新的时钟频率。 更具体地说，系统通过将时钟频率向新时钟频率转动一个增量来开始迭代，以达到中间频率而不干扰正常的存储系统操作。 接下来，系统通过完成或取消所有的飞行中或未完成的存储器系统操作并且不接受附加的存储器操作请求来通知存储器控制器来暂停正常的存储器系统操作。 在从存储器控制器接收到所有飞行中或未完成的存储器操作已经完成或终止的确认之后，系统发信号通知存储器控制器以使存储器系统内部的延迟锁定环（DLL）重新锁定到中间频率。 当DLL重新锁定到中间频率时，系统通过恢复正常的存储器系统操作来完成迭代。

    Line Reflection Reduction with Energy-Recovery Driver
    15.
    发明申请
    Line Reflection Reduction with Energy-Recovery Driver 失效
    能源回收驱动线路反射减少

    公开(公告)号：US20070126472A1

    公开(公告)日：2007-06-07

    申请号：US11673934

    申请日：2007-02-12

    申请人： Lars Svensson ,  William Athas

    发明人： Lars Svensson ,  William Athas

    IPC分类号： H03K17/16

    CPC分类号： H04L25/028 ,  H03K3/00 ,  H03K17/00 ,  H03K19/0005 ,  H03K19/0019 ,  H04L25/0278 ,  H04L25/0286 ,  H04L25/0298

    摘要： A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

    摘要翻译： 一种用于减少传输线中的反射并且在该过程期间从传输中的负载中恢复能量的系统和方法。 至少使用三个驱动信号电平。 在上升过渡期间，从第二级到第三级的转变以及在下降的转换期间从第二级到第一级的转变被定时与来自紧接在前的转换的反射信号的到达相一致。 有利地，电容器用作中间驱动信号电平的源，并且有利地有助于能量回收和保存。

    MULTIPHASE RESONANT PULSE GENERATORS
    16.
    发明申请
    MULTIPHASE RESONANT PULSE GENERATORS 失效
    多相谐振脉冲发生器

    公开(公告)号：US20070057706A1

    公开(公告)日：2007-03-15

    申请号：US11420950

    申请日：2006-05-30

    申请人： William Athas

    发明人： William Athas

    IPC分类号： H03B28/00

    CPC分类号： H03B27/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03K3/03 ,  H03K3/354

    摘要： A multiphase resonant pulse generator (74) has N groups of N−1 switches (44,46,48) which, when activated, form N paths from a power supply ((Vdc)) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N−1 switches. The signal outputs (X1,X2,X3) from each of the N paths are cross coupled to switches belonging to the other N−1 paths to active or deactivate the groups of switches.

    摘要翻译： 多相谐振脉冲发生器（74）具有N组N-1个开关（44,46,48），其在被激活时形成从电源（（Vdc））到接地或参考电压的N个路径。 这里N是大于2的正整数。每个路径包括电感（38,40,42）和N-1开关。 来自N个路径中的每一个的信号输出（X 1，X 2，X 3）与属于其它N-1路径的交换机交叉耦合，以激活或去激活该组开关。

    Flexible hermetic enclosure for implantable medical devices
    17.
    发明申请
    Flexible hermetic enclosure for implantable medical devices 有权
    用于可植入医疗器械的柔性密封外壳

    公开(公告)号：US20060217779A1

    公开(公告)日：2006-09-28

    申请号：US11088495

    申请日：2005-03-24

    申请人： Terrance Ransbury ,  William Athas ,  Arthur Gwerder

    发明人： Terrance Ransbury ,  William Athas ,  Arthur Gwerder

    IPC分类号： A61N1/375

    CPC分类号： A61N1/375 ,  A61N1/37205 ,  A61N1/37223 ,  A61N1/3968

    摘要： A flexible, hermetically sealed enclosure device allows for the controlled insertion of an implantable device into the body of a patient. A series of bellows can be used to interconnect a number of rigid containers, each containing electronic or other components necessary for the implantable device. The bellows provide flexibility, columnar strength, and torqueability (for steering), while protecting the internal components. The bellows also can be welded to the containers to form a hermetic seal that can be electrically continous, whereby standard wiring and components can be used without fear of corrosion or contamination. Such an enclosure can be used with systems such as an intravascular implantable pacing, drug delivery, or defibrillation system.

    摘要翻译： 柔性密封的封闭装置允许可植入装置被控制地插入患者体内。 可以使用一系列波纹管来连接多个刚性容器，每个容器包含可植入装置所需的电子或其他部件。 波纹管提供灵活性，柱状强度和扭矩（用于转向），同时保护内部组件。 波纹管还可以焊接到容器以形成可以电连续的气密密封，从而可以使用标准的布线和部件，而不用担心腐蚀或污染。 这样的外壳可以与诸如血管内植入式起搏，药物递送或除颤系统的系统一起使用。

    High performance clock-powered logic
    19.
    发明申请
    High performance clock-powered logic 有权
    高性能时钟供电逻辑

    公开(公告)号：US20070018689A1

    公开(公告)日：2007-01-25

    申请号：US11332852

    申请日：2006-01-13

    申请人： William Athas ,  Nestor Tzartzanis ,  Weihua Mao ,  Lena Peterson

    发明人： William Athas ,  Nestor Tzartzanis ,  Weihua Mao ,  Lena Peterson

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0019

    摘要： High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.

    摘要翻译： 高性能时钟供电逻辑运行在低于​​电源电平，并减少对更快数字逻辑电路的需求。 在优选实施例中，使用时钟缓冲器来驱动信号线。 线路的接收端连接到卡锁锁存器，优选地跟随n锁存器，随后是数字逻辑，随后是第二个n锁存器。 在替代实施例中，优选地使用互补数据信号来消除第一个n锁存器。