公开(公告)号：US11935824B2

公开(公告)日：2024-03-19

申请号：US17665749

申请日：2022-02-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L25/0652

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

公开(公告)号：US20230421163A1

公开(公告)日：2023-12-28

申请号：US18465281

申请日：2023-09-12

Applicant: Microchip Technology Incorporated

Inventor： Robert Lutwak ,  Bomy Chen

IPC: H03L7/26

CPC classification number: H03L7/26

Abstract: Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.

公开(公告)号：US11682642B2

公开(公告)日：2023-06-20

申请号：US17019768

申请日：2020-09-14

Applicant: Microchip Technology incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/49 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05019 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/386 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US20210036059A1

公开(公告)日：2021-02-04

申请号：US17074848

申请日：2020-10-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

IPC: H01L27/28

Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

公开(公告)号：US20190097027A1

公开(公告)日：2019-03-28

申请号：US16110330

申请日：2018-08-23

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/265

Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

公开(公告)号：US20250112035A1

公开(公告)日：2025-04-03

申请号：US18401902

申请日：2024-01-02

Applicant: Microchip Technology Incorporated

Inventor： Steve Nagel ,  Bomy Chen ,  Bruce Odekirk ,  Pejman Khosropour ,  Robin Liu ,  Andy Tu ,  Thomas Krutsick

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20

Abstract: A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.

公开(公告)号：US20210335627A1

公开(公告)日：2021-10-28

申请号：US17111973

申请日：2020-12-04

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Yaojian Leng ,  Bomy Chen ,  Chris Sundahl

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

Abstract: Methods are provided for forming an integrated circuit (IC) package interposer configured for back-side attachment. A porous silicon double layer is formed on a bulk silicon wafer, e.g., using a controlled anodization, the porous silicon double layer including two porous silicon layers having different porosities. An interposer is formed over the porous silicon double layer, the interposer including back-side contacts, front-side contacts, and conductive structures (e.g., vias and metal interconnect) extending through the interposer to connect selected back-side contacts with selected front-side contacts. The structure is then split at the interface between the first and second porous silicon layers of the silicon double layer, and the interposer including the second porous silicon layers is inverted and etched to remove the second silicon layer and expose the back-side contacts, such that the exposed back-side contacts can be used for back-side attachment of the interposer to a package substrate or other structure.

公开(公告)号：US10896888B2

公开(公告)日：2021-01-19

申请号：US16157826

申请日：2018-10-11

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/10 ,  H01L23/00 ,  H01L21/768

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US10861550B1

公开(公告)日：2020-12-08

申请号：US16540170

申请日：2019-08-14

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Matthew Martin

IPC: G11C11/34 ,  G11C7/00 ,  G11C16/04 ,  H01L29/423 ,  G11C16/08 ,  G11C16/34 ,  G11C16/14 ,  G11C16/10

Abstract: A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ≤6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to “RAM Flash” memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

公开(公告)号：US20190287936A1

公开(公告)日：2019-09-19

申请号：US16157826

申请日：2018-10-11

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.