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公开(公告)号：US20190341425A1
公开(公告)日：2019-11-07
申请号：US16513797
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US10460798B2
公开(公告)日：2019-10-29
申请号：US16158353
申请日：2018-10-12
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US20190206506A1
公开(公告)日：2019-07-04
申请号：US16284491
申请日：2019-02-25
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
CPC classification number: G11C29/00 , G11C13/00 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C29/52 , G11C2013/0052 , G11C2213/71 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US10269442B1
公开(公告)日：2019-04-23
申请号：US15857125
申请日：2017-12-28
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US10128315B2
公开(公告)日：2018-11-13
申请号：US15487743
申请日：2017-04-14
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Giorgio Servalli
Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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Patent Agency Ranking
公开(公告)号：US20180315474A1
公开(公告)日：2018-11-01
申请号：US15582321
申请日：2017-04-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
CPC classification number: G11C13/0004 , G11C11/005 , G11C11/5678 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/73 , G11C2213/77
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US10102905B2
公开(公告)日：2018-10-16
申请号：US15617381
申请日：2017-06-08
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US09990995B2
公开(公告)日：2018-06-05
申请号：US15854934
申请日：2017-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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公开(公告)号：US20180122860A1
公开(公告)日：2018-05-03
申请号：US15845938
申请日：2017-12-18
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
CPC classification number: H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C2213/71 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
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公开(公告)号：US20180122474A1
公开(公告)日：2018-05-03
申请号：US15854934
申请日：2017-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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