公开(公告)号：US20220069133A1

公开(公告)日：2022-03-03

申请号：US17005054

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240098970A1

公开(公告)日：2024-03-21

申请号：US17946925

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20240074141A1

公开(公告)日：2024-02-29

申请号：US17895017

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

公开(公告)号：US20230397391A1

公开(公告)日：2023-12-07

申请号：US17888467

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Scott E. Sills ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20230395723A1

公开(公告)日：2023-12-07

申请号：US18236265

申请日：2023-08-21

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78618 ,  H01L29/42384 ,  H01L27/1214 ,  G11C11/4085 ,  H01L27/127 ,  H01L27/1262 ,  H01L29/78642 ,  H01L27/1255

Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220102539A1

公开(公告)日：2022-03-31

申请号：US17035542

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L29/76 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/108 ,  H01L29/16 ,  H01L29/26 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190189515A1

公开(公告)日：2019-06-20

申请号：US15843493

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John A. Smythe ,  Haitao Liu ,  Richard J. Hill ,  Deepak Chandra Pandey

IPC: H01L21/8239 ,  H01L21/8229 ,  H01L21/8234 ,  H01L29/10 ,  G11C11/40

CPC classification number: H01L21/8239 ,  G11C11/40 ,  G11C2211/4016 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/105

Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.