-
公开(公告)号：US10684983B2
公开(公告)日：2020-06-16
申请号：US15137877
申请日：2016-04-25
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown
IPC: G06F15/80 , H03K19/17728 , G06F16/903 , G06K9/00 , G06N5/00
Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
-
公开(公告)号：US10606787B2
公开(公告)日：2020-03-31
申请号：US16519921
申请日：2019-07-23
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Inderjit S. Bains
Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
-
公开(公告)号：US20190272213A1
公开(公告)日：2019-09-05
申请号：US16418529
申请日：2019-05-21
Applicant: Micron Technology, Inc.
Inventor： David R. Brown
Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.
-
公开(公告)号：US20190259431A1
公开(公告)日：2019-08-22
申请号：US16051189
申请日：2018-07-31
Applicant: Micron Technology, Inc.
Inventor： Daniel B. Penney , Liang Chen , David R. Brown
Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.
-
公开(公告)号：US10019311B2
公开(公告)日：2018-07-10
申请号：US15280481
申请日：2016-09-29
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
CPC classification number: G06F11/1004 , G06F11/1076 , H03M13/09
Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
-
Patent Agency Ranking
公开(公告)号：US20180089019A1
公开(公告)日：2018-03-29
申请号：US15280481
申请日：2016-09-29
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
CPC classification number: G06F11/1004 , G06F11/1076 , H03M13/09
Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
-
公开(公告)号：US09886017B2
公开(公告)日：2018-02-06
申请号：US15605542
申请日：2017-05-25
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
IPC: G05B19/045 , G06F9/44 , G06F15/82 , G06F21/56 , H03K19/177 , G06N5/04
CPC classification number: G05B19/045 , G06F9/4498 , G06F15/82 , G06F21/567 , G06F2207/025 , G06N5/047 , H03K19/17724 , H03K19/17748
Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
-
公开(公告)号：US09866218B2
公开(公告)日：2018-01-09
申请号：US15362232
申请日：2016-11-28
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning , Irene J. Xu
IPC: H03K19/177 , H03K19/20 , H03K19/21 , G06F9/44 , G05B19/045 , G06F17/50 , H03K19/0175 , G06F7/00
CPC classification number: H03K19/17708 , G05B19/045 , G06F7/00 , G06F9/4498 , G06F17/5054 , H03K19/0175 , H03K19/17704 , H03K19/20 , H03K19/21 , Y02T10/82
Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
-
19.发明授权公开(公告)号：US09747242B2
公开(公告)日：2017-08-29
申请号：US15257677
申请日：2016-09-06
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Inderjit S. Bains
CPC classification number: G06F13/4027 , G06F9/4498 , G06F15/7867 , G06N3/08
Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
-
公开(公告)号：US09058465B2
公开(公告)日：2015-06-16
申请号：US14143398
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
CPC classification number: G05B19/045 , G06F9/4498 , G06F15/82 , G06F21/567 , G06F2207/025 , G06N5/047 , H03K19/17724 , H03K19/17748
Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不多于）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。
-
-
-
-
-
-
-
-
-
Search Results
129
records
(took 0.027 seconds)
