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    Active input/output expander of a memory sub-system
    12.
    发明授权
    Active input/output expander of a memory sub-system 有权

    公开(公告)号：US11132292B2

    公开(公告)日：2021-09-28

    申请号：US16709380

    申请日：2019-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Jeremy W. Butterfield ,  Sean E. Nerich ,  Dustin J. Carter

    IPC: G06F12/02 ,  G06F12/0831 ,  G06F9/54 ,  G06F12/0882 ,  G06F12/0868

    Abstract: A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the target memory die and decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. Read data is received via a memory-side interface of the active I/O expander from the memory stack including the target memory die. A signal conditioning operation is performed on the read data to generate conditioned read data. The active I/O expander sends, via the host-side interface, the conditioned read data to the host system.

    SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES
    13.
    发明申请
    SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES 有权

    公开(公告)号：US20210117115A1

    公开(公告)日：2021-04-22

    申请号：US17135476

    申请日：2020-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.

    SECURE BOOT VIA SYSTEM AND POWER MANAGEMENT MICROCONTROLLER
    14.
    发明申请
    SECURE BOOT VIA SYSTEM AND POWER MANAGEMENT MICROCONTROLLER 有权

    公开(公告)号：US20210081537A1

    公开(公告)日：2021-03-18

    申请号：US17104876

    申请日：2020-11-25

    Applicant: Micron Technology, Inc.

    Inventor： Robert W. Strong ,  Dustin J. Carter ,  Neil Levine

    IPC: G06F21/57 ,  H04L9/32 ,  G06F9/4401 ,  G06F8/60 ,  G06F9/30 ,  G06F1/26

    Abstract: A variety of applications can include apparatus and/or methods of controlling a secure boot mode for a memory system. In an embodiment, a system includes a memory component and a processing device, where the processing device is configured to control a boot process for the system to operate the memory component and perform a cryptographic verification with a host to conduct an authentication of the host. The processing device can interact with the host, in response to the authentication, to receive a setting to control the boot process in a secure boot mode. The processing can interact with another processing device of the system to store the setting and to receive a secure boot signal from the other processing device, where the secure boot signal is a signal to assert or de-assert the secure boot mode depending on a value of the setting. Additional apparatus, systems, and methods are disclosed.

    Capacitive voltage modifier for power management
    15.
    发明授权
    Capacitive voltage modifier for power management 有权

    公开(公告)号：US10482979B1

    公开(公告)日：2019-11-19

    申请号：US16119715

    申请日：2018-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley ,  Dustin J. Carter

    IPC: G11C5/14 ,  G11C16/30 ,  G06F1/26 ,  G05F1/46 ,  G06F1/28 ,  G01R19/165 ,  G11C16/10 ,  H02M3/158

    Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS
    18.
    发明公开
    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS 审中-公开

    公开(公告)号：US20240069738A1

    公开(公告)日：2024-02-29

    申请号：US17898160

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

    Capacitive voltage modifier for power management
    20.
    发明授权
    Capacitive voltage modifier for power management 有权

    公开(公告)号：US11367490B2

    公开(公告)日：2022-06-21

    申请号：US17097447

    申请日：2020-11-13

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley ,  Dustin J. Carter

    IPC: G11C16/10 ,  G11C16/30 ,  G11C5/14 ,  G06F1/26 ,  G05F1/46 ,  G06F1/28 ,  G01R19/165 ,  H02M3/158

    Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

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