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    System and method for individual addressing
    12.
    发明授权
    System and method for individual addressing 有权

    公开(公告)号：US10268602B2

    公开(公告)日：2019-04-23

    申请号：US15280611

    申请日：2016-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F12/02 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    Indirect register access method and system
    13.
    发明授权
    Indirect register access method and system 有权

    公开(公告)号：US10020033B2

    公开(公告)日：2018-07-10

    申请号：US15676796

    申请日：2017-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/30 ,  G06F9/34 ,  G06F12/06

    CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

    Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

    Adaptive content inspection
    14.
    发明授权
    Adaptive content inspection 有权

    公开(公告)号：US09684867B2

    公开(公告)日：2017-06-20

    申请号：US13928171

    申请日：2013-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Paul D. Dlugosch ,  Harold B Noyes

    IPC: G06N5/00 ,  G06F1/00 ,  G06N5/02 ,  H04L29/06

    CPC classification number: G06N5/022 ,  H04L63/0245

    Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.

    DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES
    17.
    发明申请
    DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES 审中-公开
    通过多个设备同步同步DMA并行处理单个数据流的设备，系统和方法

    公开(公告)号：US20170011094A1

    公开(公告)日：2017-01-12

    申请号：US15208419

    申请日：2016-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes

    IPC: G06F17/30 ,  G06F13/42 ,  G06F13/28

    CPC classification number: G06F17/30516 ,  G06F13/28 ,  G06F13/4282

    Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

    Abstract translation: 公开了方法和装置，其中包括例如在模式识别集群中包括一个或多个模式识别处理器的装置的系统。 可以将一个或多个模式识别处理器中的一个初始化为能够控制剩余模式识别处理器以用于数据流的同步处理的直接存储器访问主设备。

    METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE
    18.
    发明申请
    METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE 审中-公开
    在状态机发动机中使用状态矢量数据的方法和系统

    公开(公告)号：US20160320982A1

    公开(公告)日：2016-11-03

    申请号：US15206824

    申请日：2016-07-11

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0673 ,  G06F8/42 ,  G06N3/02

    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

    Abstract translation: 状态机引擎包括状态向量系统。 状态向量系统包括：输入缓冲器，被配置为从恢复缓冲器接收状态向量数据，并向状态机格状态提供状态向量数据。 状态向量系统还包括：输出缓冲器，被配置为从状态机格点接收状态向量数据，并向保存缓冲器提供状态向量数据。

    METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE
    20.
    发明申请
    METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE 有权
    用于状态机检测的方法和系统

    公开(公告)号：US20140325494A1

    公开(公告)日：2014-10-30

    申请号：US14329586

    申请日：2014-07-11

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06F9/45

    CPC classification number: G06F9/444 ,  G06F8/45 ,  G06F9/4498 ,  G06K9/00986

    Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

    Abstract translation: 一种包括包括多个存储单元的数据分析单元的设备。 存储器单元分析数据流的至少一部分并输出分析结果。 该装置还包括检测单元。 检测单元包括与门。 与门接收分析结果作为第一输入。 检测单元还包括D触发器，其包括耦合到与门的第二输入的输出。

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