公开(公告)号：US20240357837A1

公开(公告)日：2024-10-24

申请号：US18642555

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Stephen W. Russell ,  Steven P. Turini ,  Farrell M. Good ,  Kolya Yastrebenetsky ,  Nirav Vora ,  Zhao Zhao

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10

Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.

公开(公告)号：US12082513B2

公开(公告)日：2024-09-03

申请号：US17480694

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8416 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  H10B63/80 ,  H10N70/011 ,  H10N70/063 ,  H10N70/231 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8418 ,  H10N70/882 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/13 ,  G11C2213/52 ,  G11C2213/73

Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

公开(公告)号：US11545625B2

公开(公告)日：2023-01-03

申请号：US17100185

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

公开(公告)号：US20210151673A1

公开(公告)日：2021-05-20

申请号：US17100185

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

公开(公告)号：US10672981B2

公开(公告)日：2020-06-02

申请号：US16706358

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.