公开(公告)号：US20240296152A1

公开(公告)日：2024-09-05

申请号：US18591906

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Sureshkumar Shastry Vemuri

IPC: G06F16/22 ,  G06F12/02

CPC classification number: G06F16/2272 ,  G06F12/0238

Abstract: An apparatus includes a memory resource configured to store data entries in a data memory resource including a first data structure and a second data structure and a processing device coupled to the memory resource. The processing device is configured to determine a predicted address location in the first data structure, compare the predicted address location to at least one address threshold, alter the predicted address location to an altered predicted address location, determine an equivalent address location in a second data structure that is equivalent to the altered predicted address location, and write the data entry to the equivalent address location in the second data structure.

公开(公告)号：US20240281042A1

公开(公告)日：2024-08-22

申请号：US18439255

申请日：2024-02-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G06F1/20

CPC classification number: G06F1/206

Abstract: A method includes measuring, by a plurality of thermal sensors coupled to a plurality of circuit portion areas of a memory sub-system, temperature information associated with the plurality of circuit portion areas. The method further includes generating a thermal map based on the measured temperature information associated with the plurality of circuit portion areas and determining, based on the thermal map, that at least one of the circuit portion areas has greater than a threshold probability of experiencing a thermal event. The method further includes operating processing circuitry coupled to the plurality of circuit portion areas to mitigate a thermal load associated with the at least one of the circuit portion areas that has greater than the threshold probability of experiencing the thermal event.

公开(公告)号：US20240193144A1

公开(公告)日：2024-06-13

申请号：US18532552

申请日：2023-12-07

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F16/22

CPC classification number: G06F16/2255

Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.

公开(公告)号：US20240097707A1

公开(公告)日：2024-03-21

申请号：US17949635

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/1111 ,  H03M13/1575 ,  H03M13/611

Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

公开(公告)号：US20240095123A1

公开(公告)日：2024-03-21

申请号：US17949655

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad ,  Fan Zhou

IPC: G06F11/10 ,  G06F7/501 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F7/501 ,  G06F11/076 ,  G06F11/0793

Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

公开(公告)号：US20230299754A1

公开(公告)日：2023-09-21

申请号：US17696352

申请日：2022-03-16

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: H03K3/037

CPC classification number: H03K3/037

Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

公开(公告)号：US20230283386A1

公开(公告)日：2023-09-07

申请号：US17966300

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Pranjal Chauhan

IPC: H04B15/02 ,  G11C7/22

CPC classification number: H04B15/02 ,  G11C7/22

Abstract: Clock enable signals are collected and summed. The number of simultaneously enabled clock enable signals can represent switching activity within a system and can be used as an indicator for power management, noise management, etc. of such a system. Digital switching activity sensing include performance of an operation to sum a quantity of open clock gates associated with a plurality of latches that are grouped into multiple subsets of latches. An activity indication is generated based, at least in part, on a result of the operation to sum the quantity of open clock gates associated with the plurality of latches.

公开(公告)号：US20250118348A1

公开(公告)日：2025-04-10

申请号：US18787824

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G11C7/22 ,  G11C7/10

Abstract: An example method can include performing a first sensing operation associated with circuitry on a system on chip (SoC) to determine a first data value, performing a second sensing operation associated with circuitry of a sensor the SoC to determine a second data value, responsive to the first data value and the second data value being the same data value, determining that a clock margin is sufficient, and responsive to the first data value and the second data value being different data values, determining that a clock margin is insufficient. In some examples, a voltage-frequency operating combination associated with at least one operation of the SoC can be adjusted to a particular stored voltage-frequency operating combination that provides a sufficient clocking margin.

公开(公告)号：US20250117143A1

公开(公告)日：2025-04-10

申请号：US18768914

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz

IPC: G06F3/06

Abstract: An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.

公开(公告)号：US20250068231A1

公开(公告)日：2025-02-27

申请号：US18945044

申请日：2024-11-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G06F1/3296 ,  G06F1/324

Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.