公开(公告)号：US20210151111A1

公开(公告)日：2021-05-20

申请号：US17158555

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10741224B2

公开(公告)日：2020-08-11

申请号：US16518651

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Tyson M. Stichka ,  Preston Allen Thomson ,  Scott Anthony Stoller ,  Christopher Bueb ,  Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi

IPC: G11C16/06 ,  G11C5/00 ,  G11C16/26 ,  G11C16/04 ,  G11C7/04 ,  G11C16/34 ,  G11C7/10 ,  G11C11/56 ,  G11C16/10

Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

公开(公告)号：US11610632B2

公开(公告)日：2023-03-21

申请号：US17331395

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US11487612B2

公开(公告)日：2022-11-01

申请号：US17017240

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Michael G. McNeeley

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210390014A1

公开(公告)日：2021-12-16

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/0882 ,  G06F11/07 ,  G06F12/02

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20200258578A1

公开(公告)日：2020-08-13

申请号：US16856955

申请日：2020-04-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US10679704B2

公开(公告)日：2020-06-09

申请号：US16504039

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US20190324876A1

公开(公告)日：2019-10-24

申请号：US16504067

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C29/00 ,  G11C16/34 ,  G06F11/10

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US11288149B2

公开(公告)日：2022-03-29

申请号：US17065254

申请日：2020-10-07

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C16/34 ,  G11C29/00 ,  G06F11/10 ,  G11C16/04

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

公开(公告)号：US20210375387A1

公开(公告)日：2021-12-02

申请号：US16887592

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Jason Lee Nevill ,  Preston Allen Thomson ,  Chi Ming Chu ,  Sheng-Huang Lee

IPC: G11C29/50 ,  G11C5/14 ,  G11C8/08 ,  G11C7/10

Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.