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    Control arrangements and methods for accessing block oriented nonvolatile memory
    11.
    发明授权
    Control arrangements and methods for accessing block oriented nonvolatile memory 有权
    用于访问面向块的非易失性存储器的控制布置和方法

    公开(公告)号：US09489302B2

    公开(公告)日：2016-11-08

    申请号：US14721841

    申请日：2015-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Stephen P. Van Aken

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/1028 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7211 ,  Y02D10/13

    Abstract: A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes at least one module including a nonvolatile memory section that is made up of a plurality of memory devices and the module includes a bit density function to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density. The module independently performs the bit density function for the nonvolatile memory section of each module based on one or more module input parameters.

    Abstract translation: 存储器系统与主机设备数字通信，以提供主机设备的数据存储容量。 存储器系统包括至少一个模块，其包括由多个存储器件组成的非易失性存储器部分，并且该模块包括位密度函数，以将存储密度分配给每个存储器件，使得一组存储器件被配置 以高存储密度存储数据，并且另一组存储器设备被配置为以低存储密度存储数据。 该模块基于一个或多个模块输入参数独立地执行每个模块的非易失性存储器部分的位密度功能。

    MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS
    12.
    发明申请
    MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS 有权
    基于记忆质量监测的补偿方法和装置

    公开(公告)号：US20130290811A1

    公开(公告)日：2013-10-31

    申请号：US13931519

    申请日：2013-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Larry J. Koudele ,  John L. Seabury ,  Stephen P. Van Aken ,  Guy R. Wagner

    IPC: G06F11/08

    CPC classification number: G06F11/1076 ,  G06F11/08 ,  G06F11/1048 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/5671 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/3431 ,  G11C16/349 ,  H03M13/1111 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/3738 ,  H03M13/41 ,  H03M13/4138

    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

    Abstract translation: 在一个实施例中，编码器从存储器单元读取一组数据，以获得受到一个或多个失真机制影响的检索数据，作为已被存储的结果。 响应于检索到的数据生成质量度量，响应于用户数据和相关联的检索数据之间的差异而改变值。 质量监视器建立质量度量的当前值与阈值之间的关系，并且将关系监视为指示检索数据质量的劣化，并且选择性地启动错误响应。 在另一个实施例中，当监视质量度量时，校正值被迭代通过一组值，使得可以选择最紧密地接近数据的初始写入之后的质量度量值的质量度量的值 。

    Bitwise operations and apparatus in a multi-level system
    13.
    发明授权
    Bitwise operations and apparatus in a multi-level system 有权

    公开(公告)号：US10355815B2

    公开(公告)日：2019-07-16

    申请号：US15160322

    申请日：2016-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Bruce A. Liikanen ,  Stephen P. Van Aken ,  Gerald L. Cadloni ,  John L. Seabury ,  Robert B. Eisenhuth

    IPC: H04L1/00 ,  G06F11/10 ,  H03M13/25 ,  H03M13/29 ,  H03M13/35 ,  H04L29/06

    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.

    SECURE SUBSYSTEM
    15.
    发明申请
    SECURE SUBSYSTEM 审中-公开

    公开(公告)号：US20180089469A1

    公开(公告)日：2018-03-29

    申请号：US15829718

    申请日：2017-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

    IPC: G06F21/78 ,  G06F21/60

    CPC classification number: G06F21/78 ,  G06F21/60 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76

    Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

    Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
    17.
    发明授权
    Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory 有权
    具有非易失性存储器的多级系统中的高级逐位操作和装置

    公开(公告)号：US09411675B2

    公开(公告)日：2016-08-09

    申请号：US14084497

    申请日：2013-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Robert B. Eisenhuth ,  Stephen P. Van Aken

    IPC: G11C11/00 ,  G06F11/10 ,  H03M13/15 ,  H03M13/25 ,  H03M13/35 ,  H03M13/00

    CPC classification number: G06F11/1012 ,  G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/256 ,  H03M13/353 ,  H03M13/356 ,  H03M13/6362

    Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.

    Abstract translation: 数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。 数据存储在存储器中，每个存储器的每个存储单元使用多个位。 可以基于输入参数在码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。 代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。 可以执行存储和读取分数位密度。

    ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY
    18.
    发明申请
    ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY 有权
    具有非易失性存储器的多级系统中的先进的比特运算和设备

    公开(公告)号：US20140082454A1

    公开(公告)日：2014-03-20

    申请号：US14084497

    申请日：2013-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Robert B. Eisenhuth ,  Stephen P. Van Aken

    IPC: G06F11/10 ,  H03M13/25

    CPC classification number: G06F11/1012 ,  G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/256 ,  H03M13/353 ,  H03M13/356 ,  H03M13/6362

    Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

    Abstract translation: 数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。 数据存储在存储器中，每个存储器的每个存储单元使用多个位。 基于输入参数，可以在代码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。 代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。 描述存储和读取分数位密度。

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