公开(公告)号：US09202574B2

公开(公告)日：2015-12-01

申请号：US14037488

申请日：2013-09-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Zengtao Liu

IPC: G11C16/10 ,  G11C5/02 ,  G11C16/04 ,  G11C11/56 ,  G11C16/28

CPC classification number: G11C16/10 ,  G11C5/02 ,  G11C5/025 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

Abstract: In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a different source line coupled to each layer of the plurality of layers.

Abstract translation: 在一个实施例中，存储器设备可以具有多层存储单元阵列。 每个层可以具有多个存储单元串和与多个层的每个层耦合的不同的源极线。

公开(公告)号：US09036421B2

公开(公告)日：2015-05-19

申请号：US14178526

申请日：2014-02-12

Applicant: Micron Technology, Inc.

Inventor： Zengtao Liu

IPC: G11C7/10 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Abstract translation: 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线，提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如，公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元，其中串的每一端与串的另一端共享串选择门。

公开(公告)号：US20150004786A1

公开(公告)日：2015-01-01

申请号：US14486890

申请日：2014-09-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luan C. Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20140160850A1

公开(公告)日：2014-06-12

申请号：US14178526

申请日：2014-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zengtao Liu

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Abstract translation: 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线，提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如，公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元，其中串的每一端与串的另一端共享串选择门。