公开(公告)号：US12178045B2

公开(公告)日：2024-12-24

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20220157844A1

公开(公告)日：2022-05-19

申请号：US17590266

申请日：2022-02-01

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20200328222A1

公开(公告)日：2020-10-15

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/311

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20200212065A1

公开(公告)日：2020-07-02

申请号：US16812938

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US20180040626A1

公开(公告)日：2018-02-08

申请号：US15229490

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02282 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11556 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US20250167055A1

公开(公告)日：2025-05-22

申请号：US18952448

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Amitava Majumdar ,  Jeffrey D. Runia ,  Merri L. Carlson

IPC: H01L21/66

Abstract: Semiconductor devices and associated methods are shown. A device may include an array of memory cells formed on a semiconductor substrate. A device may include one or more test pattern regions located at edges adjacent to the array of memory cells, the one or more test pattern regions including, an array of parallel conductive lines; and wherein selected lines of the array of parallel conductive lines are electrically coupled to ground to detect defects during a test procedure.

公开(公告)号：US20250120085A1

公开(公告)日：2025-04-10

申请号：US18985534

申请日：2024-12-18

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20230165004A1

公开(公告)日：2023-05-25

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20220077177A1

公开(公告)日：2022-03-10

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

公开(公告)号：US20210257385A1

公开(公告)日：2021-08-19

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.