公开(公告)号：US20200075330A1

公开(公告)日：2020-03-05

申请号：US16122004

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy ,  Michael Mutch ,  Sameer Chhajed

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12

Abstract: A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US20240421226A1

公开(公告)日：2024-12-19

申请号：US18815124

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H10B12/00

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US12101946B2

公开(公告)日：2024-09-24

申请号：US18387921

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H10B99/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230042701A1

公开(公告)日：2023-02-09

申请号：US17397725

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

IPC: H01L27/11514 ,  H01L21/02

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

公开(公告)号：US20220028442A1

公开(公告)日：2022-01-27

申请号：US17496564

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC: G11C11/22 ,  H01L49/02 ,  H01L27/11502

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US11024736B2

公开(公告)日：2021-06-01

申请号：US16536590

申请日：2019-08-09

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US20200295005A1

公开(公告)日：2020-09-17

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12150312B2

公开(公告)日：2024-11-19

申请号：US17567268

申请日：2022-01-03

Applicant: Micron Technology, Inc.

Inventor： Sameer Chhajed ,  Ashonita A. Chavan ,  Mark Fischer ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B53/30 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B12/00 ,  H10B53/10

Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US12113130B2

公开(公告)日：2024-10-08

申请号：US18195480

申请日：2023-05-10

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A Khandekar

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/7841 ,  H01L21/02686 ,  H01L29/04 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/20

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US20230276635A1

公开(公告)日：2023-08-31

申请号：US18144708

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

IPC: H10B53/20 ,  H01L21/02

CPC classification number: H10B53/20 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02645

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).