摘要:
A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
摘要:
An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.
摘要:
Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.
摘要:
An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.
摘要:
A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array.
摘要:
A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.
摘要:
A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
摘要:
An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.
摘要:
A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
摘要:
A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.