公开(公告)号：US07359227B2

公开(公告)日：2008-04-15

申请号：US11202428

申请日：2005-08-11

申请人： Charles Dennison ,  Tyler Lowrey

发明人： Charles Dennison ,  Tyler Lowrey

IPC分类号： G11C5/02

CPC分类号： G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

摘要： A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

摘要翻译： 交叉点存储器包括共享地址线。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的单元。 可以使用电压偏置来选择一个单元，并且取消选择另一个单元。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造并降低成本。

公开(公告)号：US20050145850A1

公开(公告)日：2005-07-07

申请号：US11063688

申请日：2005-02-22

申请人： Charles Dennison ,  Monte Manning

发明人： Charles Dennison ,  Monte Manning

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L29/04 ,  H01L23/48 ,  H01L29/10 ,  H01L29/15

CPC分类号： H01L29/6675 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78648 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

摘要翻译： 电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。 这样可用于制造薄膜晶体管和其他电路。

公开(公告)号：US5844254A

公开(公告)日：1998-12-01

申请号：US858863

申请日：1997-05-19

申请人： Monte Manning ,  Charles Dennison

发明人： Monte Manning ,  Charles Dennison

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

摘要翻译： 本公开包括使用薄膜晶体管的优选半导体晶体管器件以及形成这种器件的优选方法。 具体地，形成具有顶表面的底部薄膜晶体管栅极。 在薄膜晶体管栅极附近提供绝缘填充物，至少与薄膜晶体管栅极顶表面一样高，并且随后平整以提供与薄膜晶体管栅极相邻的大致平面的绝缘表面。 平面绝缘表面基本上与薄膜晶体管栅极顶表面共面。 然后在薄膜晶体管栅极上方并在相邻的平面绝缘表面上形成平面半导体薄膜。 掺杂薄膜以形成薄膜晶体管的源区和漏极区，薄膜晶体管是由薄膜晶体管栅极选通的。

公开(公告)号：US07348620B2

公开(公告)日：2008-03-25

申请号：US11706000

申请日：2007-02-13

申请人： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

发明人： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L3/113

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

摘要翻译： 在一些情况下，通过将相变材料层形成为平面构型，相变存储器可以表现出改善的性能和较低的成本。 可以在相变材料层的下方设置加热器，以适当地加热材料以引起相变。 加热器可以耦合到适当的导体。

公开(公告)号：US20060120136A1

公开(公告)日：2006-06-08

申请号：US11202428

申请日：2005-08-11

申请人： Charles Dennison ,  Tyler Lowrey

发明人： Charles Dennison ,  Tyler Lowrey

IPC分类号： G11C11/00

CPC分类号： G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

摘要： A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

摘要翻译： 交叉点存储器包括共享地址线。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的单元。 可以使用电压偏置来选择一个单元，并且取消选择另一个单元。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造并降低成本。

公开(公告)号：US5411909A

公开(公告)日：1995-05-02

申请号：US82401

申请日：1993-06-23

申请人： Monte Manning ,  Charles Dennison

发明人： Monte Manning ,  Charles Dennison

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

摘要翻译： 本公开包括使用薄膜晶体管的优选半导体晶体管器件以及形成这种器件的优选方法。 具体地，形成具有顶表面的底部薄膜晶体管栅极。 在薄膜晶体管栅极附近提供绝缘填充物，至少与薄膜晶体管栅极顶表面一样高，并且随后平整以提供与薄膜晶体管栅极相邻的大致平面的绝缘表面。 平面绝缘表面基本上与薄膜晶体管栅极顶表面共面。 然后在薄膜晶体管栅极上方并在相邻的平面绝缘表面上形成平面半导体薄膜。 掺杂薄膜以形成薄膜晶体管的源区和漏极区，薄膜晶体管是由薄膜晶体管栅极选通的。

公开(公告)号：US20100283029A1

公开(公告)日：2010-11-11

申请号：US12454002

申请日：2009-05-11

申请人： Charles Dennison ,  Wolodymyr Czubatyj ,  Jeff Fournier ,  Tom Latowski ,  James Reed ,  Regino Sandoval

发明人： Charles Dennison ,  Wolodymyr Czubatyj ,  Jeff Fournier ,  Tom Latowski ,  James Reed ,  Regino Sandoval

IPC分类号： H01L45/00 ,  H01L21/06 ,  H01L21/20

CPC分类号： H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.

摘要翻译： 存储器包括多层沉积的存储器材料。 在沉积后续存储材料层之前，在至少一层沉积的存储材料上进行蚀刻。

公开(公告)号：US20080064200A1

公开(公告)日：2008-03-13

申请号：US11983188

申请日：2007-11-07

申请人： Brian Johnson ,  Charles Dennison

发明人： Brian Johnson ,  Charles Dennison

IPC分类号： H01L21/44

CPC分类号： G06F21/125 ,  G06F21/10 ,  H01L45/06 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1666

摘要： Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.

摘要翻译： 简而言之，根据本发明的实施例，提供了制造相变存储器的方法。 该方法可以包括形成接触相变材料的侧壁表面和底表面的第一电极。 该方法还可以包括形成接触相变材料的顶表面的第二电极。

公开(公告)号：US20080020508A1

公开(公告)日：2008-01-24

申请号：US11904557

申请日：2007-09-27

申请人： Charles Dennison

发明人： Charles Dennison

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1675

摘要： A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.

摘要翻译： 相变存储器可以以减少氧气穿过覆盖在下电极上的硫属化物层的方式形成。 这种渗透可能导致下部电极的氧化，这对性能有不利影响。 在一个这样的实施例中，通过覆盖的上电极层的蚀刻可以在到达覆盖所述硫族化物层的层之前停止。 然后，可以在高温氧等离子体中使用用于这种蚀刻的光致抗蚀剂。 只有在这样的等离子体处理完成之后，去除了上层，最终暴露了硫族化物。

公开(公告)号：US20060234469A1

公开(公告)日：2006-10-19

申请号：US11409134

申请日：2006-04-21

申请人： David Dickerson ,  Richard Lane ,  Charles Dennison ,  Kunal Parekh ,  Mark Fischer ,  John Zahurak

发明人： David Dickerson ,  Richard Lane ,  Charles Dennison ,  Kunal Parekh ,  Mark Fischer ,  John Zahurak

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

摘要翻译： 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。