公开(公告)号：US20070035028A1

公开(公告)日：2007-02-15

申请号：US11499059

申请日：2006-08-04

Applicant: Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

Inventor： Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

IPC: H01L23/52

CPC classification number: H01L27/1104 ,  H01L21/76808 ,  H01L27/0207 ,  H01L27/11

Abstract: Integrated circuit memory devices include an integrated circuit substrate and a plurality of lower wiring lines on the substrate and extending in a first direction. An interlayer insulating layer is on the plurality of lower wiring lines. An upper damascene wiring line is in an upper portion of the interlayer insulating layer and extending in a second direction, different from the first direction, to extend over the plurality of lower wiring lines. The upper damascene wiring line has protruded regions extending therefrom in a direction different from the second direction, the protruded regions extending over respective underlying ones of the lower wiring lines. A first via extends through the interlayer insulating layer under a first of the protruded regions and connects the upper damascene wiring line to a corresponding underlying first one of the plurality of wiring lines. A second via extends through the interlayer insulating layer under a second of the protruded regions and connects the upper damascene wiring line to a corresponding underlying second one of the plurality of wiring lines.

Abstract translation: 集成电路存储器件包括集成电路基板和在基板上的多个下布线，并沿第一方向延伸。 层间绝缘层位于多个下布线上。 上部镶嵌线路位于层间绝缘层的上部，并且沿与第一方向不同的第二方向延伸，在多条下部布线上延伸。 上部镶嵌线具有沿与第二方向不同的方向从其延伸的突出区域，突出区域延伸到下部布线的下方。 第一通孔延伸穿过位于第一突出区域的层间绝缘层，并将上镶嵌布线连接到多个布线中相应的下面的第一布线。 第二通孔在第二突出区域的下方延伸穿过层间绝缘层，并将上部镶嵌线路连接到多条布线中相应的下面的第二布线。

公开(公告)号：US06953745B2

公开(公告)日：2005-10-11

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

公开(公告)号：US06498092B2

公开(公告)日：2002-12-24

申请号：US09780830

申请日：2001-02-09

Applicant: Kyung-tae Lee ,  Seong-ho Liu

Inventor： Kyung-tae Lee ,  Seong-ho Liu

IPC: H01L214763

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.

Abstract translation: 公开了一种具有双镶嵌线结构的半导体器件及其制造方法。 半导体器件和方法解决了部分或完全闭合的接触孔的常规问题，并且通过使用蚀刻停止层，由于其介电常数的增加而抑制了层间绝缘层中的寄生电容的增加 。 为了实现这一点，在其上形成有第一导电图案的半导体衬底上形成第一层间绝缘层。 接下来，相对于第一层间绝缘层具有蚀刻选择比的蚀刻停止图案部分地形成在特定区域中。 此后，形成第二层间绝缘层和由铜制成的第二导电层。

公开(公告)号：US07768128B2

公开(公告)日：2010-08-03

申请号：US11499059

申请日：2006-08-04

Applicant: Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

Inventor： Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/1104 ,  H01L21/76808 ,  H01L27/0207 ,  H01L27/11

Abstract: Integrated circuit memory devices include an integrated circuit substrate and a plurality of lower wiring lines on the substrate and extending in a first direction. An interlayer insulating layer is on the plurality of lower wiring lines. An upper damascene wiring line is in an upper portion of the interlayer insulating layer and extending in a second direction, different from the first direction, to extend over the plurality of lower wiring lines. The upper damascene wiring line has protruded regions extending therefrom in a direction different from the second direction, the protruded regions extending over respective underlying ones of the lower wiring lines. A first via extends through the interlayer insulating layer under a first of the protruded regions and connects the upper damascene wiring line to a corresponding underlying first one of the plurality of wiring lines. A second via extends through the interlayer insulating layer under a second of the protruded regions and connects the upper damascene wiring line to a corresponding underlying second one of the plurality of wiring lines.

Abstract translation: 集成电路存储器件包括集成电路基板和在基板上的多个下布线，并沿第一方向延伸。 层间绝缘层位于多个下布线上。 上部镶嵌线路位于层间绝缘层的上部，并且沿与第一方向不同的第二方向延伸，在多条下部布线上延伸。 上部镶嵌线具有沿与第二方向不同的方向从其延伸的突出区域，突出区域延伸到下部布线的下方。 第一通孔延伸穿过位于第一突出区域的层间绝缘层，并将上镶嵌布线连接到多个布线中相应的下面的第一布线。 第二通孔延伸穿过第二突出区域之间的层间绝缘层，并将上部镶嵌布线连接到多条布线中相应的下面的第二布线。

公开(公告)号：US07679123B2

公开(公告)日：2010-03-16

申请号：US11684865

申请日：2007-03-12

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC: H01L29/94

CPC classification number: H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Abstract translation: 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

公开(公告)号：US20070184610A1

公开(公告)日：2007-08-09

申请号：US11733711

申请日：2007-04-10

Applicant: Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

Inventor： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

公开(公告)号：US07208791B2

公开(公告)日：2007-04-24

申请号：US11168126

申请日：2005-06-28

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC: H01L27/108

CPC classification number: H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Abstract translation: 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

公开(公告)号：US20050247968A1

公开(公告)日：2005-11-10

申请号：US11168126

申请日：2005-06-28

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108

CPC classification number: H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Abstract translation: 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

公开(公告)号：US06940114B2

公开(公告)日：2005-09-06

申请号：US10657490

申请日：2003-09-08

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108

CPC classification number: H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Abstract translation: 集成电路器件包括在集成电路衬底上的集成电路衬底和金属 - 绝缘体 - 金属（MIM）电容器的导电下电极层。 电介质层位于下电极层上，MIM电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间电介质层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

公开(公告)号：US20050024979A1

公开(公告)日：2005-02-03

申请号：US10901239

申请日：2004-07-29

Applicant: Yoon-hae Kim ,  Kyung-tae Lee ,  Seong-ho Liu

Inventor： Yoon-hae Kim ,  Kyung-tae Lee ,  Seong-ho Liu

IPC: H01L21/768 ,  G11C8/02 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04

CPC classification number: H01L28/40 ,  H01L28/75

Abstract: A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.

Abstract translation: 使用镶嵌工艺制造MIM电容器和互连结构的方法。 MIM电容器和第一互连结构可以以相等的深度形成。