中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.016 seconds)

    PROGRAMMABLE INTEGRATED CIRCUIT AND CONTROL DEVICE
    11.
    发明申请
    PROGRAMMABLE INTEGRATED CIRCUIT AND CONTROL DEVICE 审中-公开

    公开(公告)号：US20200251496A1

    公开(公告)日：2020-08-06

    申请号：US16648757

    申请日：2018-09-14

    Applicant: NEC Corporation

    Inventor： Makoto MIYAMURA ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

    IPC: H01L27/118 ,  G11C11/56 ,  G11C13/00 ,  G06F30/327

    Abstract: A programmable integrated circuit includes: a crossbar switch constituted of a plurality of first wires arranged in a first direction, a plurality of second wires arranged in a second direction intersecting the first direction, and resistance change type elements connecting the first wires and the second wires; an output buffer group constituted of at least two output buffers operating with different drive powers; and a logic circuit group constituted of at least one logic circuit connected to an output of the second wire. The output buffers in the output buffer group is connected to an input of any one of a plurality of the first wires.

    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200234760A1

    公开(公告)日：2020-07-23

    申请号：US16489912

    申请日：2018-02-28

    Applicant: NEC CORPORATION

    Inventor： Makoto MIYAMURA ,  Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

    IPC: G11C13/00

    Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

    LOGIC INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    13.
    发明申请
    LOGIC INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190028101A1

    公开(公告)日：2019-01-24

    申请号：US16061701

    申请日：2017-01-16

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

    IPC: H03K19/003 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G06F11/07

    Abstract: An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

    DESIGN ASSISTANCE SYSTEM, DESIGN ASSISTANCE METHOD, AND PROGRAM RECORDING MEDIUM
    15.
    发明申请
    DESIGN ASSISTANCE SYSTEM, DESIGN ASSISTANCE METHOD, AND PROGRAM RECORDING MEDIUM 审中-公开

    公开(公告)号：US20200380190A1

    公开(公告)日：2020-12-03

    申请号：US16766467

    申请日：2018-11-21

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

    IPC: G06F30/343 ,  G06F30/347

    Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

    LOGIC INTEGRATED CIRCUIT
    16.
    发明申请
    LOGIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200336145A1

    公开(公告)日：2020-10-22

    申请号：US16957973

    申请日：2019-01-21

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

    IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/1776 ,  G11C13/00

    Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

    INTEGRATED CIRCUIT
    19.
    发明申请
    INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190253057A1

    公开(公告)日：2019-08-15

    申请号：US16333317

    申请日：2017-09-11

    Applicant: NEC CORPORATION

    Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Ayuka TADA ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

    IPC: H03K19/177 ,  G11C13/00 ,  G06F17/50

    Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

Patent Agency Ranking