-
公开(公告)号：US20210098345A1
公开(公告)日：2021-04-01
申请号：US16988741
申请日：2020-08-10
Applicant: Novatek Microelectronics Corp.
Inventor： Chiao-Ling Huang , Tai-Hung Lin
IPC: H01L23/498 , H01L23/00 , H01L21/48 , H01L23/12
Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
-
公开(公告)号：US10770368B2
公开(公告)日：2020-09-08
申请号：US16055183
申请日：2018-08-06
Applicant: Novatek Microelectronics Corp.
Inventor： Wen-Ching Huang , Tai-Hung Lin
IPC: H01L23/29 , H01L23/367 , H01L23/373 , H01L23/00 , H01L23/495 , H01L21/48
Abstract: A chip on film package includes a base film, a chip and a heat-dissipation structure. The base film includes a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and has a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis. The heat-dissipation structure includes a covering portion. The covering portion at least partially covers the chip, exposes a side surface of the chip, and has a first length along the first axis and a second length along the second axis being longer than the chip width of the chip. The side surface connects a top surface and a bottom surface of the chip. A heat-dissipation structure is also provided.
-
公开(公告)号：US10043737B2
公开(公告)日：2018-08-07
申请号：US15336821
申请日：2016-10-28
Applicant: Novatek Microelectronics Corp.
Inventor： Wen-Ching Huang , Tai-Hung Lin
IPC: H01L23/29 , H01L23/495 , H01L21/56 , H01L23/31 , H01L23/36 , H01L23/498 , H01L21/48 , H01L23/00
Abstract: A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.
-
公开(公告)号：US10777498B2
公开(公告)日：2020-09-15
申请号：US15821846
申请日：2017-11-24
Applicant: Novatek Microelectronics Corp.
Inventor： Chiao-Ling Huang , Tai-Hung Lin
IPC: H01L23/498 , H01L23/00 , H01L21/48 , H01L23/12
Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
-
公开(公告)号：US09881892B2
公开(公告)日：2018-01-30
申请号：US15412072
申请日：2017-01-23
Applicant: Novatek Microelectronics Corp.
Inventor： Jung-Fu Hsu , Tai-Hung Lin , Chang-Tien Tsai
CPC classification number: H01L24/06 , H01L23/50 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L27/0292 , H01L27/0296 , H01L2224/02166 , H01L2224/04042 , H01L2224/05088 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0612 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48132 , H01L2224/48464 , H01L2224/48465 , H01L2224/49113 , H01L2924/00014 , H01L2924/01029 , H01L2924/2064 , H01L2924/30205 , H01L2924/00 , H01L2924/00015 , H01L2224/43
Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.
-
Patent Agency Ranking
公开(公告)号：US20170192453A1
公开(公告)日：2017-07-06
申请号：US15257937
申请日：2016-09-07
Applicant: Novatek Microelectronics Corp.
Inventor： Wen-Ching Huang , Shu-Huan Hsieh , Tai-Hung Lin , Feng-Ting Pai
CPC classification number: G06F1/163 , G09G3/001 , G09G2300/0421 , H05K1/0216 , H05K1/028 , H05K1/11 , H05K1/147 , H05K1/18 , H05K1/189
Abstract: A wearable device with a chip on film package structure is provided. The wearable device with the chip on film package structure includes a display device and a chip device. The display device includes a display area and a non-display area. The non-display area includes a bonding area. The chip device is bonded to the display device via the chip on film package structure. The chip device is configured to drive the display device to display images. The chip on film package structure includes a film having a first end and a second end. The chip device is located on the film, and the first end of the film is bonded to the bonding area of the display device.
-
公开(公告)号：US20170133343A1
公开(公告)日：2017-05-11
申请号：US15412072
申请日：2017-01-23
Applicant: Novatek Microelectronics Corp.
Inventor： Jung-Fu Hsu , Tai-Hung Lin , Chang-Tien Tsai
CPC classification number: H01L24/06 , H01L23/50 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L27/0292 , H01L27/0296 , H01L2224/02166 , H01L2224/04042 , H01L2224/05088 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0612 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48132 , H01L2224/48464 , H01L2224/48465 , H01L2224/49113 , H01L2924/00014 , H01L2924/01029 , H01L2924/2064 , H01L2924/30205 , H01L2924/00 , H01L2924/00015 , H01L2224/43
Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.
-
公开(公告)号：US20150194399A1
公开(公告)日：2015-07-09
申请号：US14666322
申请日：2015-03-24
Applicant: Novatek Microelectronics Corp.
Inventor： Tai-Hung Lin , Chang-Tien Tsai
CPC classification number: H01L24/05 , H01L23/49 , H01L23/60 , H01L24/06 , H01L24/42 , H01L24/45 , H01L24/48 , H01L27/0248 , H01L2224/02166 , H01L2224/04042 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48465 , H01L2924/00014 , H01L2924/01029 , H01L2924/2064 , H01L2924/00 , H01L2924/00015 , H01L2224/43 , H01L2224/45099
Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically coupled to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically coupled to the second circuit. The second internal bonding pad is electrically coupled to the first internal bonding pad via the bonding wire. The external bonding pad is electrically coupled to the first internal bonding pad.
Abstract translation: 提供一种集成电路装置，包括基板，第一内部接合焊盘，第二内部焊盘，外部焊盘和接合线。 第一电路和第二电路嵌入在基板中。 第一内部接合焊盘设置在基板的表面上并电耦合到第一电路。 第二内部接合焊盘设置在基板的表面上并电耦合到第二电路。 第二内部接合焊盘经由接合线电耦合到第一内部接合焊盘。 外部接合焊盘电耦合到第一内部接合焊盘。
-
公开(公告)号：US09041201B2
公开(公告)日：2015-05-26
申请号：US14062899
申请日：2013-10-25
Applicant: Novatek Microelectronics Corp.
Inventor： Tai-Hung Lin , Chang-Tien Tsai
CPC classification number: H01L24/05 , H01L23/49 , H01L23/60 , H01L24/06 , H01L24/42 , H01L24/45 , H01L24/48 , H01L27/0248 , H01L2224/02166 , H01L2224/04042 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48465 , H01L2924/00014 , H01L2924/01029 , H01L2924/2064 , H01L2924/00 , H01L2924/00015 , H01L2224/43
Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically coupled to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically coupled to the second circuit. The second internal bonding pad is electrically coupled to the first internal bonding pad via the bonding wire. The external bonding pad is electrically coupled to the first internal bonding pad.
Abstract translation: 提供一种集成电路装置，包括基板，第一内部接合焊盘，第二内部焊盘，外部焊盘和接合线。 第一电路和第二电路嵌入在基板中。 第一内部接合焊盘设置在基板的表面上并电耦合到第一电路。 第二内部接合焊盘设置在基板的表面上并电耦合到第二电路。 第二内部接合焊盘经由接合线电耦合到第一内部接合焊盘。 外部接合焊盘电耦合到第一内部接合焊盘。
-
公开(公告)号：US20190067168A1
公开(公告)日：2019-02-28
申请号：US15821846
申请日：2017-11-24
Applicant: Novatek Microelectronics Corp.
Inventor： Chiao-Ling Huang , Tai-Hung Lin
IPC: H01L23/498 , H01L23/12 , H01L21/48 , H01L23/00
Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.021 seconds)
