公开(公告)号：US20160269002A1

公开(公告)日：2016-09-15

申请号：US14644637

申请日：2015-03-11

Applicant: NVIDIA Corporation

Inventor： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC: H03K3/012 ,  H03K19/21 ,  H03K3/037

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract translation: 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。

公开(公告)号：US09219480B2

公开(公告)日：2015-12-22

申请号：US14170342

申请日：2014-01-31

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Ying Huang

IPC: H03K3/00 ,  H03K19/003 ,  H03K3/037 ,  G06F1/10

CPC classification number: H03K19/003 ,  G06F1/10 ,  H03K3/0372

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。

公开(公告)号：US09071240B2

公开(公告)日：2015-06-30

申请号：US13626100

申请日：2012-09-25

Applicant: Nvidia Corporation

Inventor： Hank Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: H03L5/00 ,  H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017509 ,  H03K19/018507

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract translation: 本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。 在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和 被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。

公开(公告)号：US08866528B2

公开(公告)日：2014-10-21

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K3/289

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定输入信号传送到第二输出信号。

公开(公告)号：US20140167828A1

公开(公告)日：2014-06-19

申请号：US13715969

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract translation: 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。

公开(公告)号：US10181842B2

公开(公告)日：2019-01-15

申请号：US14945377

申请日：2015-11-18

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Lingfei Deng ,  Hwong-Kwo Lin

IPC: H03K3/356 ,  H03K3/037

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

公开(公告)号：US10120028B2

公开(公告)日：2018-11-06

申请号：US15257781

申请日：2016-09-06

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

公开(公告)号：US09842631B2

公开(公告)日：2017-12-12

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA Corporation

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/12 ,  G11C11/4091

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

公开(公告)号：US09438213B2

公开(公告)日：2016-09-06

申请号：US14723356

申请日：2015-05-27

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

公开(公告)号：US09435861B2

公开(公告)日：2016-09-06

申请号：US13663379

申请日：2012-10-29

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract translation: 介绍了锁存器的系统和方法。 在一个实施例中，系统包括传播组件，数据传播组件和控制组件中的扫描。 传播分量中的扫描可操作以在数值扫描和再循环值之间进行选择。 数据传播组件可操作以在数据值和从传播组件中的扫描转发的结果之间进行选择，其中数据传播组件的结果作为再循环值被转发到传播组件中的扫描。 控制组件可操作以通过传播组件和数据传播组件中的扫描来控制选择的指示。