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    REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS
    11.
    发明申请
    REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS 有权
    在解决存储器访问错误时重新进行内存交易

    公开(公告)号：US20140281263A1

    公开(公告)日：2014-09-18

    申请号：US14109678

    申请日：2013-12-17

    Applicant: NVIDIA CORPORATION

    Inventor： James Leroy DEMING ,  Jerome F. DULUK, Jr. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsay EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

    IPC: G06F12/10 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

    Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

    Abstract translation: 本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。 当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。 重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。 当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。 有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

    MIGRATING PAGES OF DIFFERENT SIZES BETWEEN HETEROGENEOUS PROCESSORS
    13.
    发明申请
    MIGRATING PAGES OF DIFFERENT SIZES BETWEEN HETEROGENEOUS PROCESSORS 有权
    异构处理器之间的不同尺寸的移动页

    公开(公告)号：US20160357482A1

    公开(公告)日：2016-12-08

    申请号：US15243909

    申请日：2016-08-22

    Applicant: NVIDIA Corporation

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY ,  James M. VAN DYKE

    IPC: G06F3/06 ,  G06F12/1009

    CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

    Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

    Abstract translation: 本发明的一个实施例提出了一种用于将存储器页从第一存储器迁移到第二存储器的计算机实现的方法。 该方法包括确定由第一存储器支持的第一页大小。 该方法还包括确定由第二存储器支持的第二页大小。 该方法还包括基于与存储器页相关联的页面状态目录中的条目来确定存储器页面的使用历史。 该方法还包括基于第一页面大小，第二页面大小和使用历史来在第一存储器和第二存储器之间迁移存储器页面。

    FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM
    14.
    发明申请
    FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM 有权
    通过一个统一的虚拟内存系统中的滑动窗口来进行帧缓冲器访问

    公开(公告)号：US20140281365A1

    公开(公告)日：2014-09-18

    申请号：US14105015

    申请日：2013-12-12

    Applicant: NVIDIA CORPORATION

    Inventor： John MASHEY ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Jerome F. DULUK, JR. ,  Brian FAHS

    IPC: G06F12/10

    CPC classification number: G06F3/0622 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/656 ,  G06F2212/684

    Abstract: One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.

    Abstract translation: 本发明的一个实施例是一种存储器子系统，其包括跟踪与存储器页组的滑动窗口相关联的存储器访问的滑动窗口跟踪器。 当滑动窗口跟踪器检测到与滑动窗口内的存储器页面组相关联的访问操作时，滑动窗口跟踪器设置与存储器页面组相关联的参考位，并且被包括在表示对存储器页面的访问的参考向量中 在滑动窗口内的组。 基于参考位的值，滑动窗口跟踪器使选择已经从第一存储器废弃到第二存储器的存储器页组中的存储器页。 因为滑动窗口跟踪器调谐驻留在第一存储器中的存储器页面以反映存储器访问模式，所以提高了存储器子系统的整体性能。

    MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM
    15.
    发明申请
    MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
    用于统一的虚拟内存系统的移动方案

    公开(公告)号：US20140281358A1

    公开(公告)日：2014-09-18

    申请号：US14055382

    申请日：2013-10-16

    Applicant: NVIDIA Corporation

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

    Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，产生第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

    COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM
    16.
    发明申请
    COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
    统一的虚拟内存系统中的通用点

    公开(公告)号：US20140281357A1

    公开(公告)日：2014-09-18

    申请号：US14055367

    申请日：2013-10-16

    Applicant: NVIDIA Corporation

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

    Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，生成第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

    FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM
    17.
    发明申请
    FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
    用于解决统一的虚拟内存系统中的页面故障的故障缓冲区

    公开(公告)号：US20140281256A1

    公开(公告)日：2014-09-18

    申请号：US14055356

    申请日：2013-10-16

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

    IPC: G06F11/07 ,  G06F12/12

    CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

    Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，产生第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM
    18.
    发明申请
    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM 有权
    PCIE交通跟踪硬件在一个统一的虚拟内存系统

    公开(公告)号：US20140281110A1

    公开(公告)日：2014-09-18

    申请号：US14101246

    申请日：2013-12-09

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. DULUK, Jr. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

    IPC: G06F12/08 ,  G06F13/40

    CPC classification number: G06F13/404 ,  G06F12/0806 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1041

    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

    Abstract translation: 公开了用于跟踪统一虚拟存储器系统中的存储器页面访问的技术。 访问跟踪单元检测由第一处理器生成的用于访问第二处理器的存储器系统中的存储器页面的存储器页面访问。 访问跟踪单元确定高速缓存存储器是否包括用于存储器页面的条目。 如果是这样，则访问跟踪单元增加相关联的访问计数器。 否则，访问跟踪单元尝试在高速缓冲存储器中找到可用于分配的未使用的条目。 如果是，则访问跟踪单元将第二条目与存储器页面相关联，并将与第二条目相关联的访问计数器设置为初始值。 否则，访问跟踪单元选择高速缓冲存储器中的有效条目; 清除相关的有效位; 将条目与记忆页相关联; 并初始化相关的访问计数器。

    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
    19.
    发明申请
    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20170371802A9

    公开(公告)日：2017-12-28

    申请号：US14011643

    申请日：2013-08-27

    Applicant: NVIDIA CORPORATION

    Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/301

    Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

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