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    Method and apparatus for selecting optimum levels for in-system programmable charge pumps
    11.
    发明授权
    Method and apparatus for selecting optimum levels for in-system programmable charge pumps 失效
    用于选择系统内可编程电荷泵的最佳电平的方法和装置

    公开(公告)号：US5889701A

    公开(公告)日：1999-03-30

    申请号：US99160

    申请日：1998-06-18

    申请人： Sunae Kang ,  Rafael G. San Luis, Jr. ,  Derek R. Curd ,  Ronald J. Mack

    发明人： Sunae Kang ,  Rafael G. San Luis, Jr. ,  Derek R. Curd ,  Ronald J. Mack

    IPC分类号： G06F11/00 ,  G11C16/30 ,  G11C29/44 ,  G11C29/50 ,  G11C16/04

    CPC分类号： G06F11/006 ,  G11C16/30 ,  G11C29/44 ,  G11C29/50

    摘要： A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

    摘要翻译： 一个新颖的测试程序用于确定CPLD中闪存阵列的最佳可编程电荷泵电平。 根据本发明的方法，自动化测试仪通过电荷泵代码的所有组合进行步骤，并尝试以每个电压组合组合闪速存储器。 对于每个组合，测试结果（通过或失败）被记录并存储到地图或数组中。 通过泵代码窗口的中心作为起始参考点。 下一步是验证与起始参考点对应的泵代码组合相关的实际电压电平。 将参考泵代码装载到器件中，并测量相应的闪存单元电压电平。 如果测量的电压电平不在优选范围内，则测试仪将通过调节泵代码自动调整到优选范围。

    Partial reconfiguration of a programmable logic device using an on-chip processor
    12.
    发明授权
    Partial reconfiguration of a programmable logic device using an on-chip processor 有权
    使用片上处理器对可编程逻辑器件进行部分重新配置

    公开(公告)号：US06907595B2

    公开(公告)日：2005-06-14

    申请号：US10319051

    申请日：2002-12-13

    申请人： Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck ,  Stephen W. Trynosky ,  Jeffrey V. Lindholm ,  Trevor J. Bauer

    发明人： Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck ,  Stephen W. Trynosky ,  Jeffrey V. Lindholm ,  Trevor J. Bauer

    IPC分类号： G06F15/78 ,  G06F17/50

    CPC分类号： G06F15/7867

    摘要： A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

    摘要翻译： 使用由处理器控制的读 - 修改 - 写入方案来部分地重新配置可编程逻辑器件，例如现场可编程门阵列。 部分重新配置包括（1）将一组配置数据值加载到可编程逻辑器件的配置存储器阵列中，从而配置可编程逻辑器件; （2）从配置存储器阵列读取配置数据值的第一帧; （3）修改配置数据值的第一帧中的配置数据值的子集，由此创建配置数据值的第一修改帧; 和（4）用配置数据值的第一修改帧重写配置存储器阵列中的配置数据值的第一帧，从而部分地重新配置可编程逻辑器件。 读取，修改和重写的步骤在处理器的控制下执行。

    Negative voltage detector
    13.
    发明授权
    Negative voltage detector 有权
    负电压检测器

    公开(公告)号：US06278327B1

    公开(公告)日：2001-08-21

    申请号：US09374473

    申请日：1999-08-13

    申请人： Derek R. Curd ,  Fariba Farahanchi

    发明人： Derek R. Curd ,  Fariba Farahanchi

    IPC分类号： H03F316

    CPC分类号： G11C16/30 ,  G11C5/143

    摘要： A negative voltage detector is disclosed wherein a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider of the present invention allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

    摘要翻译： 公开了一种负电压检测器，其中使用电阻分压器电路将负电压转换成标准CMOS逻辑低或逻辑高值。 由本发明的负分压器消耗的小面积允许多个器件放置在逻辑器件内，而不会消耗逻辑器件上的大量面积。 此外，放置的多个器件可以通过简单调整器件组件来检测不同的负电压阈值。

    Method of minimizing power use in programmable logic devices
    14.
    发明授权
    Method of minimizing power use in programmable logic devices 有权
    最小化可编程逻辑器件中的功耗的方法

    公开(公告)号：US06172518B2

    公开(公告)日：2001-01-09

    申请号：US09360111

    申请日：1999-07-23

    申请人： Jesse H. Jenkins, IV. ,  Jeffrey H. Seltzer ,  Derek R. Curd

    发明人： Jesse H. Jenkins, IV. ,  Jeffrey H. Seltzer ,  Derek R. Curd

    IPC分类号： G06F738

    CPC分类号： H03K19/17784

    摘要： A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed. No specific input/output pins are required; in fact, no external connections are required at all, though one or more may be used as inputs to the control function block logic. In some embodiments, power management can be accomplished using internal, on-chip signals alone. The pin-locking capabilities (compatibility) of conventional PLD designs are not affected and all function blocks remain identical, preserving maximum design flexibility for users.

    摘要翻译： 一种使用可编程连接和废料逻辑来最小化可编程逻辑器件（PLD）中功率使用的方法，以创建通用的电源管理方案。 可以关闭PLD中的单个产品术语，从而节省电力，而不会导致现有技术中看到的上电和稳定时间延迟。 电源管理不限于任何一个功能块，除非经过编程，否则整个设备也不能关闭电源。 存在于PLD中的所有常规逻辑功能对于电源管理元件是可用的，在一个实施例中允许将标准功能块编程为操作作为控制功能块。 该逻辑功能包括但不限于内部反馈，组合功能和寄存器功能。 由于使用了从用户编程和小型可编程连接遗留下来的废料逻辑资源，所以需要最小的附加芯片表面积。 不需要特定的输入/输出引脚; 事实上，根本不需要外部连接，尽管一个或多个可以用作控制功能块逻辑的输入。 在一些实施例中，可以仅使用内部片上信号来实现功率管理。 传统PLD设计的引脚锁定功能（兼容性）不受影响，所有功能块保持不变，为用户保留最大的设计灵活性。

    Low-voltage input/output circuit with high voltage tolerance
    15.
    发明授权
    Low-voltage input/output circuit with high voltage tolerance 失效
    具有高电压容差的低压输入/输出电路

    公开(公告)号：US6121795A

    公开(公告)日：2000-09-19

    申请号：US31389

    申请日：1998-02-26

    申请人： Derek R. Curd ,  Hy V. Nguyen

    发明人： Derek R. Curd ,  Hy V. Nguyen

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/0175

    CPC分类号： H03K19/018592 ,  H03K19/00315

    摘要： An input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal of an integrated circuit device, such as a Programmable Logic Device (PLD). The I/O circuit includes pull-up and pull-down transistors for generating output signals on the I/O terminal in an output mode, and an isolation transistor for limiting the voltage level transmitted to the pull-up transistor from the I/O terminal in an input mode. The isolation transistor is formed with a thicker gate oxide and a longer channel length than that of the pull-up and pull-down transistors, thereby allowing the isolation transistor to withstand voltages greater than Vcc of the PLD without damage. The isolation transistor is controlled using a charge pump provided on the PLD for programming non-volatile memory cells (e.g., EPROM, EEPROM or flash EPROM cells). The isolation transistor is produced during the same process steps used to produce high voltage transistors associated with the non-volatile memory cells.

    摘要翻译： 用于在诸如可编程逻辑器件（PLD）的集成电路器件的I / O端子上传输输入信号或从其接收输入信号的输入/输出（I / O）电路。 I / O电路包括用于在输出模式下在I / O端子上产生输出信号的上拉和下拉晶体管，以及用于限制从I / O传输到上拉晶体管的电压电平的隔离晶体管 终端处于输入模式。 隔离晶体管形成有比上拉和下拉晶体管更厚的栅极氧化物和更长的沟道长度，从而允许隔离晶体管承受大于PLD的Vcc的电压而不损坏。 使用在PLD上提供的用于编程非易失性存储器单元（例如，EPROM，EEPROM或闪存EPROM单元）的电荷泵来控制隔离晶体管。 在用于产生与非易失性存储器单元相关联的高电压晶体管的相同工艺步骤期间产生隔离晶体管。

    Negative voltage detector
    17.
    发明授权
    Negative voltage detector 有权
    负电压检测器

    公开(公告)号：US06549016B1

    公开(公告)日：2003-04-15

    申请号：US09896158

    申请日：2001-06-28

    申请人： Derek R. Curd ,  Fariba Farahanchi

    发明人： Derek R. Curd ,  Fariba Farahanchi

    IPC分类号： G01R3108

    CPC分类号： G11C16/30 ,  G11C5/143

    摘要： A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

    摘要翻译： 使用包括电阻分压器电路的负电压检测器将负电压转换为标准CMOS逻辑低电平或逻辑高电平值。 负分压器消耗的小面积允许多个器件放置在逻辑器件中，而不会消耗逻辑器件上的大量面积。 此外，放置的多个器件可以通过简单调整器件组件来检测不同的负电压阈值。

    Boundary-scan register cell with bypass circuit
    19.
    发明授权
    Boundary-scan register cell with bypass circuit 有权
    带旁路电路的边界扫描寄存器单元

    公开(公告)号：US06314539B1

    公开(公告)日：2001-11-06

    申请号：US09176659

    申请日：1998-10-21

    申请人： Neil G. Jacobson ,  Derek R. Curd

    发明人： Neil G. Jacobson ,  Derek R. Curd

    IPC分类号： G01R3128

    CPC分类号： G01R31/318541

    摘要： A Boundary-Scan register (BSR) cell including a bypass circuit for selectively routing data signals around the data shift register of the BSR cell so that the BSR cell can be effectively removed from a BSR chain during Boundary-Scan Test procedures involving IEEE Standard 1149.1 compliant integrated circuits. In one embodiment, the BSR cell includes a bypass MUX having a first input terminal connected to a test data input (TDI) terminal of the BSR cell, a second input terminal connected to an output terminal of the shift register, and an output terminal connected to the test data output (TDO) terminal. The BSR cell operates in a “normal” mode (i.e., included in the BSR chain) when the bypass MUX is controlled to pass data signals output from the shift register to the TDO terminal. In contrast, the BSR cell is selectively bypassed (i.e., removed from the BSR chain) when the bypass MUX is controlled to pass the TDI signal to the TDO terminal. The BSR cell also includes mode control MUX having a first input terminal connected to receive a MODE signal generated by a Boundary-Scan TAP controller, a second input terminal connected to an OFF (disable) signal source, and an output terminal connected to the output MUX of the BSR cell. When the BSR cell operates in the “normal”, the mode control MUX is controlled to pass the MODE signal to the output MUX. In contrast, when the BSR cell is selectively bypassed, the OFF signal is passed to the output MUX.

    摘要翻译： 一种边界扫描寄存器（BSR）单元，包括用于选择性地在BSR单元的数据移位寄存器周围数据信号路由的旁路电路，使得可以在涉及IEEE标准1149.1的边界扫描测试程序期间将BSR单元有效地从BSR链中移除 兼容的集成电路。 在一个实施例中，BSR单元包括旁路MUX，其具有连接到BSR单元的测试数据输入（TDI）端的第一输入端，连接到移位寄存器的输出端的第二输入端和连接的输出端 到测试数据输出（TDO）端子。 当旁路MUX被控制以将从移位寄存器输出的数据信号传递到TDO终端时，BSR单元工作在“正常”模式（即包括在BSR链中）。 相反，当旁路MUX被控制以将TDI信号传递到TDO终端时，BSR单元被选择性地旁路（即从BSR链移除）。 BSR单元还包括模式控制MUX，其具有被连接以接收由边界扫描TAP控制器产生的MODE信号的第一输入端子，连接到OFF（禁止）信号源的第二输入端子以及连接到输出端的输出端子 BSR单元的MUX。 当BSR单元工作在“正常”时，控制模式控制MUX将MODE信号传递到输出MUX。 相反，当选择性地旁路BSR单元时，OFF信号被传递到输出MUX。

    High-voltage power multiplexor
    20.
    发明授权
    High-voltage power multiplexor 失效
    高压电源多路复用器

    公开(公告)号：US5650672A

    公开(公告)日：1997-07-22

    申请号：US533413

    申请日：1995-09-25

    申请人： Derek R. Curd

    发明人： Derek R. Curd

    IPC分类号： H03K17/0416 ,  H03K17/693 ,  H01H35/00

    CPC分类号： H03K17/04163 ,  H03K17/693 ,  Y10T307/50 ,  Y10T307/647 ,  Y10T307/675 ,  Y10T307/696 ,  Y10T307/702 ,  Y10T307/724 ,  Y10T307/729 ,  Y10T307/858

    摘要： A multiplexor having a multiplexor control input terminal for selectively providing one of a plurality of conductor voltage levels to a conductor. The multiplexor includes a first switch, which is coupled to the conductor, for providing a first conductor voltage level to the conductor. A second switch is also included and coupled to the conductor for providing a second conductor voltage level to the conductor. To provide a selective discharge path for the conductor during switching, the multiplexor further includes a third switch coupled to the conductor. A discharge circuit is also provided and coupled to the conductor and the third switch for sensing the voltage level of the conductor to turn on the third switch as necessary at the early stage of switching among conductor voltage levels.

    摘要翻译： 一种具有多路复用器控制输入端的复用器，用于选择性地向导体提供多个导体电压电平中的一个。 多路复用器包括耦合到导体的第一开关，用于向导体提供第一导体电压电平。 还包括第二开关并耦合到导体，以向导体提供第二导体电压电平。 为了在切换期间为导体提供选择性放电路径，多路复用器还包括耦合到导体的第三开关。 还提供放电电路并耦合到导体和第三开关，用于感测导体的电压电平，以在导体电压电平之间的切换的早期阶段根据需要接通第三开关。