公开(公告)号：US6011717A

公开(公告)日：2000-01-04

申请号：US666849

申请日：1996-06-19

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/14 ,  G11C16/00

CPC classification number: G11C16/0433 ,  G11C16/14

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract translation: 在字线和位线中以矩阵形式组织EEPROM。 存储单元被放置在这些线的交点处。 这些单元包括浮栅存储晶体管。 创建具有分开的位线但共享字线的单元组。 每组连接到组选择晶体管。 组选择晶体管选择性地将存储晶体管的控制栅极连接到控制线，控制线提供用于实现存储晶体管的编程，擦除或读取的电位。

公开(公告)号：US5796297A

公开(公告)日：1998-08-18

申请号：US666733

申请日：1996-06-17

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

CPC classification number: H03K17/693 ,  Y10T307/696 ,  Y10T307/832 ,  Y10T307/858

Abstract: A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively to one of the input terminals, the first and second input terminals being connected to the output terminal by means of a first transistor and a second transistor and the circuit comprising control means for the production, as a function of the command signal, of the control voltages applied to the control gates of the transistors for the selective connection of the output terminal to one of the input terminals.

Abstract translation: 选择器开关电路包括用于接收正电压的输入端子，用于接收负电压的输入端子，用于接收第一命令逻辑信号的命令输入端子和输出端子以提供输出电压。 输出被选择性地连接到一个输入端，第一和第二输入端通过第一晶体管和第二晶体管连接到输出端，并且该电路包括作为指令的函数的用于产生的控制装置 施加到晶体管的控制栅极的控制电压的信号，用于选择性地将输出端子连接到输入端子之一。

公开(公告)号：US5760638A

公开(公告)日：1998-06-02

申请号：US664083

申请日：1996-06-13

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/06 ,  H02M3/07 ,  H03K3/02 ,  H03K3/06

CPC classification number: H02M3/073

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract translation: 相位发生器电路循环地产生第一对相位信号和第二对相位信号，包括第一电路以产生每对相位信号的第一相位，这些第一相位信号是不重叠的，并且在电压 0和电压VCC，以及用于产生的第二和第三电路，分别来自第一对的第二相和第二对相位信号的第二相的第一相位信号，这些第二相位信号是不重叠的 第一相信号并在负电压-V和电压VCC之间切换。 本发明适用于负荷电压型负压发电机电路的试点。

公开(公告)号：US07321516B2

公开(公告)日：2008-01-22

申请号：US11063651

申请日：2005-02-22

Applicant: Alberto Jose' Di Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Salvatore Zompi

Inventor： Alberto Jose' Di Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Salvatore Zompi

IPC: G11C15/00

CPC classification number: G11C5/147 ,  G11C16/0441 ,  G11C16/24 ,  G11C16/30 ,  G11C29/846

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract translation: 一种用于存储单元存储元件的偏置结构，用于设置存储单元存储元件的寄存电极处的工作电压。 偏置结构包括耦合到寄存电极的偏置晶体管，并且适于基于在偏置晶体管的控制电极处接收的偏置电压来设置工作电压;以及偏置电压发生器，用于产生偏置电压。 偏置电压发生器包括适应偏置晶体管的阈值电压的轨道变化的反馈电压调节结构，以便保持存储单元存储元件的入门电极处的工作电压对于操作条件变化基本上是稳定的。

公开(公告)号：US07170790B2

公开(公告)日：2007-01-30

申请号：US11061104

申请日：2005-02-18

Applicant: Nicolas Demange ,  Antonino Conte ,  Salvatore Preciso ,  Alfredo Signorello

Inventor： Nicolas Demange ,  Antonino Conte ,  Salvatore Preciso ,  Alfredo Signorello

IPC: G11C16/06

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V−); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135′; N3s, 135″) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135′; 135″). A memory device using the sensing circuit and a method are also provided.

Abstract translation: 一种用于感测电流的感测电路（120），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于将输入电流转换成对应的输入电压（V- ）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 以及用于比较输入和比较电压的至少一个电压比较器（140）和用于产生比较电流的比较电流产生电路（N 3 s，135; N 3 s，135'; N 3 s，135“） 基于参考电流（Ir）。 比较电流产生电路包括至少一个电压发生器（135; 135'; 135“）。 还提供了使用感测电路的存储器件和方法。

公开(公告)号：US06930907B2

公开(公告)日：2005-08-16

申请号：US10414252

申请日：2003-04-14

Applicant: Giampiero Sberno ,  Salvatore Torrisi ,  Nicolas Demange

Inventor： Giampiero Sberno ,  Salvatore Torrisi ,  Nicolas Demange

IPC: G11C7/18 ,  G11C11/22

CPC classification number: G11C7/18 ,  G11C11/22 ,  G11C2211/4013

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract translation: 铁电半导体存储器包括包括至少一行存储器单元的存储器单元的布置。 至少一行的存储器单元与该布置的相应字线相关联。 存储单元的布置包括从与至少一行相关联的字线分支的多个本地字线，每个本地字线连接到线路的相应组的存储器单元。 选择性连接装置允许选择性地将本地字线之一连接到相应的字线。 存储单元的布置还包括多个局部板偏置线，每个板偏置线与相应组的存储单元相关联，用于选择性地驱动各组的存储单元。

公开(公告)号：US5652720A

公开(公告)日：1997-07-29

申请号：US573897

申请日：1995-12-18

Applicant: Maxence Aulas ,  Alessandro Brigati ,  Nicolas Demange ,  Marc Guedj

Inventor： Maxence Aulas ,  Alessandro Brigati ,  Nicolas Demange ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3431 ,  G11C16/3418

Abstract: The present invention concerns an electrically programmable memory and a method for writing within this memory. In order to avoid the degradation of information in a memory cell following a number of write cycles in the other cells of the same row, the present invention includes a sequence to be carried out before each write cycle of a word within a row. A systematic reading of all the words of a row by using three different read reference potentials is performed in order to find a cell that gives non-compatibility results between any two of the three read cycles. The words of the row are stored in a register. If a non-compatible result is found, which indicates a degradation of information in the row, a systematic re-write of all the words of the row is carried out.

Abstract translation: 本发明涉及一种电可编程存储器和一种用于在该存储器内写入的方法。 为了避免在同一行的其他单元中的多个写周期之后的存储单元中的信息的劣化，本发明包括在行内的单词的每个写入周期之前要执行的序列。 执行通过使用三个不同的读取参考电位对一行中的所有单词的系统读取，以便找到在三个读取周期中的任何两个之间给出不兼容结果的单元。 行中的单词存储在一个寄存器中。 如果发现不兼容的结果，表示该行中信息的恶化，则执行该行中所有字的系统重新写入。

公开(公告)号：US08264257B2

公开(公告)日：2012-09-11

申请号：US12828052

申请日：2010-06-30

Applicant: Nicolas Demange

Inventor： Nicolas Demange

IPC: H03K3/00

CPC classification number: H03K17/10 ,  H03K19/018528

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract translation: 本公开涉及一种集成电路，其包括数据缓冲器电路，该数据缓冲电路包括耦合到接触焊盘和第三和第四晶体管的第一和第二晶体管。 第一偏置电压施加在第三晶体管的导通端子上，第二偏置电压施加在第四晶体管的导通端上。 在第一晶体管的控制端上施加小于第二偏置电压的第三偏置电压，并且在第二晶体管的控制端上施加大于第一偏置电压的第四偏置电压。 特别适用于生产所谓“高速”USB端口的应用。

公开(公告)号：US20110001558A1

公开(公告)日：2011-01-06

申请号：US12828052

申请日：2010-06-30

Applicant: Nicolas Demange

Inventor： Nicolas Demange

IPC: G05F1/10

CPC classification number: H03K17/10 ,  H03K19/018528

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract translation: 本公开涉及一种集成电路，其包括数据缓冲器电路，该数据缓冲电路包括耦合到接触焊盘和第三和第四晶体管的第一和第二晶体管。 第一偏置电压施加在第三晶体管的导通端子上，第二偏置电压施加在第四晶体管的导通端上。 在第一晶体管的控制端上施加小于第二偏置电压的第三偏置电压，并且在第二晶体管的控制端上施加大于第一偏置电压的第四偏置电压。 特别适用于生产所谓“高速”USB端口的应用。

公开(公告)号：US07301837B2

公开(公告)日：2007-11-27

申请号：US11291478

申请日：2005-11-30

Applicant: Nicolas Demange

Inventor： Nicolas Demange

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/02

Abstract: A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

Abstract translation: 非易失性存储器包括提供对存储器单元的访问的字线，将字线对应于输入地址的激活信号应用于字线的转换器，转换器通过降低其电压电平来再现输出上的激活信号，以及编码 电路，其包括具有低于输出的电压电平的开关阈值的晶体管，并被耦合，以便如果该字线是唯一被激活的字线，则产生专用于激活字线的输出地址，使得测试电路产生 如果输入地址与输出地址不同，则出现错误信号。 在这样的结构中，可以减少由测试电路占用的硅的面积。