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    Multi-pass rendering in a screen space pipeline
    11.
    发明授权
    Multi-pass rendering in a screen space pipeline 有权

    公开(公告)号：US10430989B2

    公开(公告)日：2019-10-01

    申请号：US14952400

    申请日：2015-11-25

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Hakura ,  Cynthia Allison ,  Dale Kirkland ,  Jeffrey Bolz ,  Yury Uralsky ,  Jonah Alben

    IPC: G06T17/00 ,  G06T15/00 ,  G06T11/40

    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

    Deferred shading graphics processing unit, geometry data structure and method of performing anti-aliasing in deferred shading
    13.
    发明授权
    Deferred shading graphics processing unit, geometry data structure and method of performing anti-aliasing in deferred shading 有权
    延迟着色图形处理单元，几何数据结构和在延迟着色中执行抗锯齿的方法

    公开(公告)号：US09390540B2

    公开(公告)日：2016-07-12

    申请号：US13725721

    申请日：2012-12-21

    Applicant: Nvidia Corporation

    Inventor： Yury Uralsky

    IPC: G06T15/00

    CPC classification number: G06T15/005

    Abstract: A deferred shading GPU, geometry data structure and method. One embodiment of the geometry data structure is found in a graphics processing subsystem operable to render a scene having a pixel represented by samples. The graphics processing subsystem includes: (1) a memory configured to store a geometry data structure associated with the pixel containing surface fragment coverage masks associated with the samples, and (2) a GPU configured to employ the surface fragment coverage masks to carry out deferred shading on the pixel.

    Abstract translation: 延迟着色GPU，几何数据结构和方法。 几何数据结构的一个实施例在可操作以渲染具有由样本表示的像素的场景的图形处理子系统中找到。 图形处理子系统包括：（1）存储器，被配置为存储与包含与样本相关联的表面片段覆盖掩码的像素相关联的几何数据结构，以及（2）配置为使用表面片段覆盖掩码来执行延迟的GPU 在像素上阴影

    SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING PROCESSES INVOLVING AT LEAST ONE PRIMITIVE IN A GRAPHICS PROCESSOR, UTILIZING A DATA STRUCTURE
    16.
    发明申请
    SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING PROCESSES INVOLVING AT LEAST ONE PRIMITIVE IN A GRAPHICS PROCESSOR, UTILIZING A DATA STRUCTURE 审中-公开
    用于在图形处理器中至少涉及一个主体的执行过程的系统，方法和计算机程序产品，利用数据结构

    公开(公告)号：US20140267260A1

    公开(公告)日：2014-09-18

    申请号：US13843981

    申请日：2013-03-15

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Sami Hakura ,  Yury Uralsky ,  Tyson Bergland ,  Eric Brian Lum ,  Jerome F. Duluk, JR. ,  Henry Packard Moreton

    IPC: G09G5/14

    CPC classification number: G06T15/005 ,  G09G5/14 ,  H04N13/128 ,  H04N2013/0081

    Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.

    Abstract translation: 提供了一种系统，方法和计算机程序产品，用于执行利用数据结构在图形处理器中涉及至少一个原语的处理。 在操作中，数据结构与至少一个原语相关联。 另外，利用数据结构，在图形处理器中执行涉及至少一个图元的多个处理。 此外，多个处理包括选择至少一个表面或其部分以呈现或选择多个视口中的至少一个的视口中的至少一个。

    Programming model for resource-constrained scheduling
    19.
    发明授权
    Programming model for resource-constrained scheduling 有权

    公开(公告)号：US12197954B2

    公开(公告)日：2025-01-14

    申请号：US17204508

    申请日：2021-03-17

    Applicant: NVIDIA CORPORATION

    Inventor： Yury Uralsky ,  Henry Moreton ,  Matthijs de Smedt ,  Lei Yang

    IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

    Abstract: The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.

    Techniques for representing and processing geometry within a graphics processing pipeline
    20.
    发明授权
    Techniques for representing and processing geometry within a graphics processing pipeline 有权

    公开(公告)号：US10600229B2

    公开(公告)日：2020-03-24

    申请号：US15881564

    申请日：2018-01-26

    Applicant: NVIDIA Corporation

    Inventor： Ziyad Hakura ,  Yury Uralsky ,  Christoph Kubisch ,  Pierre Boudier ,  Henry Moreton

    IPC: G06T15/00 ,  G06T17/20 ,  G06T15/04 ,  G06T17/10 ,  G06T15/80

    Abstract: In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images via a shading program. In operation, the parallel processor causes a first set of execution threads to execute the shading program on a first portion of the input mesh to generate first geometry stored in an on-chip memory. The parallel processor also causes a second set of execution threads to execute the mesh shading program on a second portion of the input mesh to generate second geometry stored in the on-chip memory. Subsequently, the parallel processor reads the first geometry and the second geometry from the on-chip memory, and performs operations on the first geometry and the second geometry to generate a rendered image derived from the input mesh. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

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