SiGe Photodiode for Crosstalk Reduction

    公开(公告)号:US20220399393A1

    公开(公告)日:2022-12-15

    申请号:US17343553

    申请日:2021-06-09

    Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

    PIXEL LAYOUT WITH PHOTODIODE REGION PARTIALLY SURROUNDING CIRCUITRY

    公开(公告)号:US20220352220A1

    公开(公告)日:2022-11-03

    申请号:US17243024

    申请日:2021-04-28

    Abstract: An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

    IMAGE SENSOR WITH PARTIALLY ENCAPSULATING ATTENUATION LAYER

    公开(公告)号:US20210202554A1

    公开(公告)日:2021-07-01

    申请号:US16730137

    申请日:2019-12-30

    Abstract: A pixel cell includes a first photodiode, a second photodiode, a first deep trench isolation region, a second deep trench isolation region, a buffer oxide layer, and a light attenuation layer. The attenuation layer partially encapsulates the first photodiode by extending laterally from the first deep trench isolation region to the second deep trench isolation region between the semiconductor material and the buffer oxide layer.

    IMAGE SENSOR WITH SPLIT PIXEL STRUCTURE AND METHOD OF MANUFACTURING THEREOF

    公开(公告)号:US20210151482A1

    公开(公告)日:2021-05-20

    申请号:US16687660

    申请日:2019-11-18

    Abstract: An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.

    OPERATION METHOD TO MITIGATE LAG ISSUE WITH HIGH K METAL-INSULATOR-METAL (MIM) CAPACITOR

    公开(公告)号:US20250126373A1

    公开(公告)日:2025-04-17

    申请号:US18488492

    申请日:2023-10-17

    Abstract: Image sensors with improved memory effect are disclosed herein. In one embodiment, a method for reducing image lag associated with a pixel included in a plurality of pixels is described. The pixel includes a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a dual floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source. The lateral overflow integration capacitor is further coupled to a pixel reference voltage source through a reset transistor. Operation of the pixel comprises an idle period and an integration period after the idle period. The method also includes configuring the lateral overflow integration capacitor to be either zero-biased or forward-biased during the idle period.

    High K metal-insulator-metal (MIM) capacitor network for lag mitigation

    公开(公告)号:US12177589B2

    公开(公告)日:2024-12-24

    申请号:US18154770

    申请日:2023-01-13

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

    LOFIC CIRCUIT FOR IN PIXEL METAL-INSULATOR-METAL(MIM) CAPACITOR LAG CORRECTION AND ASSOCIATED CORRECTION METHODS

    公开(公告)号:US20240244344A1

    公开(公告)日:2024-07-18

    申请号:US18154715

    申请日:2023-01-13

    CPC classification number: H04N25/59 H01L27/14612 H01L27/14643 H04N25/771

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network is coupled between the reset transistor and a bias voltage source. The LOFIC network includes a main LOFIC coupled between the reset transistor and the bias voltage source, and a plurality of subordinate capacitor-switch pairs, each including a subordinate LOFIC and a switch transistor coupled to the subordinate LOFIC. Each of the plurality of subordinate capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

    MULTILAYER REFLECTIVE STACK FOR REDUCING CROSSTALK IN SPLIT PIXEL IMAGE SENSORS

    公开(公告)号:US20240186353A1

    公开(公告)日:2024-06-06

    申请号:US18076084

    申请日:2022-12-06

    Abstract: An image sensor comprising a semiconductor substrate, a plurality of photodiodes, a multilayer reflective stack, and a dielectric layer is disclosed. The plurality of photodiodes is disposed within the semiconductor substrate and includes a first photodiode and a second photodiode adjacent to the first photodiode. The multilayer reflective stack comprises a first material having a first refractive index and a second material having a second refractive index. The dielectric layer has a third refractive index and is disposed between the first photodiode and the multilayer reflective stack. The first material is disposed between the second material and the dielectric layer. The first refractive index is greater than the second refractive index and the third refractive index.

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