公开(公告)号：US20150138410A1

公开(公告)日：2015-05-21

申请号：US14086832

申请日：2013-11-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Jian Guo

IPC: H04N5/355 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/35572 ,  H04N5/3745 ,  H04N5/37457 ,  H04N5/378 ,  H04N9/045

Abstract: A method of controlling a pixel array includes reading out image data from pixel cells of a row i of the of the pixel array with second transfer control signals that are coupled to be received by transfer transistors included in the pixels cells of the row of the of the pixel array that is being read out. Exposure times for pixel cells are independently controlled in other rows of the pixel array that are not being read out with first transfer control signals coupled to be received by transfer transistors included in the pixel cells in the other rows of the of the pixel array that are not being read out while the image data is read out from the pixel cells of row i of the pixel array.

Abstract translation: 控制像素阵列的方法包括：通过第二传输控制信号从像素阵列的行i的像素单元读出图像数据，第二传输控制信号被耦合以由包含在该行的像素阵列中的像素单元中的传输晶体管接收 正在读出的像素阵列。 像素单元的曝光时间在像素阵列的其他行中被独立地控制，该第一行不被第一传输控制信号读出，该第一传输控制信号被耦合以由像素阵列的其它行中的像素单元中包含的传输晶体管接收 在从像素阵列的行i的像素单元读出图像数据的同时不读出。

公开(公告)号：US09030584B2

公开(公告)日：2015-05-12

申请号：US13846418

申请日：2013-03-18

Applicant: OmniVision Technologies, Inc.

Inventor： Tiejun Dai

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/357 ,  H01L27/146 ,  H01L31/062 ,  H01L31/113

CPC classification number: H04N5/3577 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689

Abstract: A process including forming an a backside-illuminated (BSI) image sensor in a substrate, the image sensor including a pixel array formed in or near a front surface of the substrate and one or more circuit blocks formed in the substrate near the pixel array, each circuit block including at least one support circuit. An interconnect layer is formed on the front surface of the substrate that includes a dielectric within which are embedded traces and vias, wherein the traces and vias electrically couple the pixel array to at least one of the one or more support circuits. An isolation trench is formed surrounding at least one of the one or more circuit blocks to isolate the pixel array and other circuit blocks from noise generated by the at least one support circuit within the circuit block surrounded by the isolation trench. Other embodiments are disclosed and claimed.

Abstract translation: 一种方法，包括在衬底中形成背面照射（BSI）图像传感器，所述图像传感器包括形成在所述衬底的前表面中或附近的像素阵列和形成在所述衬底附近的所述像素阵列的一个或多个电路块， 每个电路块包括至少一个支撑电路。 在衬底的前表面上形成互连层，该衬底的内表面上包括一个电介质，其中嵌有迹线和通孔，其中迹线和通孔将像素阵列电耦合到一个或多个支撑电路中的至少一个。 围绕所述一个或多个电路块中的至少一个形成隔离沟槽，以将像素阵列和其它电路块与由隔离沟槽包围的电路块内的至少一个支撑电路产生的噪声隔离开。 公开和要求保护其他实施例。

公开(公告)号：US20150115131A1

公开(公告)日：2015-04-30

申请号：US14065275

申请日：2013-10-28

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A.G. Webster ,  Tiejun Dai

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/369 ,  H04N5/37455 ,  H04N5/378

Abstract: An example imaging sensor system includes a Single-Photon Avalanche Diode (SPAD) imaging array formed in a first semiconductor layer of a first wafer. The SPAD imaging array includes an N number of pixels, each including a SPAD region formed in a front side of the first semiconductor layer. The first wafer is bonded to a second wafer at a bonding interface between a first interconnect layer of the first wafer and the second interconnect layer of the second wafer. An N number of digital counters are formed in a second semiconductor layer of the second wafer. Each of the digital counters are configured to count output pulses generated by a respective SPAD region.

Abstract translation: 示例性成像传感器系统包括形成在第一晶片的第一半导体层中的单光子雪崩二极管（SPAD）成像阵列。 SPAD成像阵列包括N个像素，每个像素包括形成在第一半导体层的前侧的SPAD区域。 第一晶片在第一晶片的第一互连层和第二晶片的第二互连层之间的接合界面处接合到第二晶片。 N个数字计数器形成在第二晶片的第二半导体层中。 每个数字计数器被配置为对相应SPAD区域产生的输出脉冲进行计数。

公开(公告)号：US20150070542A1

公开(公告)日：2015-03-12

申请号：US14543483

申请日：2014-11-17

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Junzhao Lei

IPC: H04N5/335 ,  H04N5/232

CPC classification number: H04N5/335 ,  H01L27/14601 ,  H04N5/23241 ,  H04N5/369 ,  H04N5/378

Abstract: An image sensor system includes an image sensor and a host controller. The image sensor includes a power input terminal, a data terminal, a clock input terminal, and a ground terminal. The host controller is coupled to the power input terminal to provide power to the image sensor, the data terminal to receive analog image data from the image sensor, the clock input terminal to provide a clock signal to the image sensor, and the ground terminal. The ground terminal serves as a common reference between the image sensor and one or more circuits of the host controller. The system also includes logic that is configured to transfer the analog image data from the image sensor to the host controller through the data terminal of the image sensor and to transfer one or more digital control signals between the image sensor and the host controller through the data terminal.

Abstract translation: 图像传感器系统包括图像传感器和主机控制器。 图像传感器包括电源输入端子，数据端子，时钟输入端子和接地端子。 主机控制器耦合到电源输入端以向图像传感器提供电力，数据终端接收来自图像传感器的模拟图像数据，时钟输入端子以向图像传感器和接地端子提供时钟信号。 接地端子用作图像传感器和主机控制器的一个或多个电路之间的公共参考。 该系统还包括被配置为通过图像传感器的数据端将模拟图像数据从图像传感器传送到主机控制器并且通过数据传送图像传感器和主机控制器之间的一个或多个数字控制信号的逻辑 终奌站。

公开(公告)号：US20140225998A1

公开(公告)日：2014-08-14

申请号：US14253699

申请日：2014-04-15

Applicant: Omnivision Technologies, Inc.

Inventor： Tiejun Dai ,  Junzhao Lei

IPC: H04N5/376

CPC classification number: H04N5/2354 ,  H01L27/14601 ,  H04N5/3532 ,  H04N2005/2255

Abstract: A multiple image sensor image acquisition system includes a clock control unit to generate a synchronization clock signal. The synchronization clock signal has a prolonged constant cycle during which the synchronization clock signal is held at a constant level for a period of time corresponding to multiple clock cycles. A first image sensor is coupled with the clock control unit to receive the synchronization clock signal and has a first synchronization unit that is operable to synchronize operation for the first image sensor based on detection of an end of the prolonged constant cycle. A second image sensor is coupled with the clock control unit to receive the synchronization clock signal and has a second synchronization unit that is operable to synchronize operation for the second image sensor based on detection of the end of the prolonged constant cycle. The image sensors are synchronized operationally.

Abstract translation: 多图像传感器图像采集系统包括产生同步时钟信号的时钟控制单元。 同步时钟信号具有延长的恒定周期，在此期间同步时钟信号在对应于多个时钟周期的时间段内保持在恒定电平。 第一图像传感器与时钟控制单元耦合以接收同步时钟信号，并且具有第一同步单元，其可操作以基于对延长的恒定周期的结束的检测来同步第一图像传感器的操作。 第二图像传感器与时钟控制单元耦合以接收同步时钟信号，并且具有第二同步单元，其可操作以基于延长的恒定周期的结束的检测来同步第二图像传感器的操作。 图像传感器在操作上是同步的。

公开(公告)号：US12200388B2

公开(公告)日：2025-01-14

申请号：US18313957

申请日：2023-05-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Zhe Gao ,  Tomas Geurts ,  Ling Fu ,  Tiejun Dai

IPC: H04N25/78

Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

公开(公告)号：US20240381002A1

公开(公告)日：2024-11-14

申请号：US18313957

申请日：2023-05-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Zhe Gao ,  Tomas Geurts ,  Ling Fu ,  Tiejun Dai

IPC: H04N25/78

Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

公开(公告)号：US11658202B2

公开(公告)日：2023-05-23

申请号：US17066200

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Hiroaki Ebihara ,  Sang Joo Lee ,  Rui Wang ,  Hiroki Ui

IPC: H04N5/232 ,  H01L27/146 ,  H01L27/148 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77 ,  H01L27/14621

Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

公开(公告)号：US11652131B2

公开(公告)日：2023-05-16

申请号：US17066277

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sang Joo Lee ,  Rui Wang ,  Hiroaki Ebihara ,  Tiejun Dai ,  Hiroki Ui

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/374 ,  H01L27/148 ,  H04N9/04 ,  H04N5/347 ,  H04N5/3745

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N5/347 ,  H04N5/378 ,  H04N5/3745 ,  H04N9/0451 ,  H04N9/04551 ,  H01L27/14621

Abstract: A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

公开(公告)号：US11516419B2

公开(公告)日：2022-11-29

申请号：US17156290

申请日：2021-01-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Shoushun Chen ,  Zhe Gao

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/345 ,  H04N5/355 ,  H04N5/378

Abstract: An event driven pixel includes a photodiode configured to photogenerate charge in response to incident light received from an external scene. A photocurrent to voltage converter is coupled to the photodiode to convert photocurrent generated by the photodiode to a voltage. A filter amplifier is coupled to the photocurrent to voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent to voltage converter. A threshold comparison stage is coupled to the filter amplifier to compare the filtered and amplified signal received from the filter amplifier with thresholds to asynchronously detect events in the external scene in response to the incident light. A digital time stamp generator is coupled to asynchronously generate a digital time stamp in response to the events asynchronously detected in the external scene by the threshold comparison stage.